| Method for manufacturing a semiconductor device having an alignment feature formed using an N-type dopant and a wet oxidation process B Hu, SP Pendharkar, BA Wofford, JM Ramirez US Patent 7,435,659, 2008 | 220 | 2008 |
| LDMOS power device with oversized dwell CY Tsai, TR Efland, S Pendharkar, JP Erdeljac, J Mitros, JP Smith, ... US Patent 6,424,005, 2002 | 98 | 2002 |
| A rugged LDMOS for LBC5 technology P Hower, J Lin, S Pendharkar, B Hu, J Arch, J Smith, T Efland Proceedings. ISPSD'05. The 17th International Symposium on Power …, 2005 | 94 | 2005 |
| System and method for making a LDMOS device with electrostatic discharge protection SP Pendharkar, JS Brodsky US Patent 7,414,287, 2008 | 87 | 2008 |
| Drain extend MOS transistor with improved breakdown robustness SP Pendharkar US Patent 6,960,807, 2005 | 74 | 2005 |
| Resurf LDMOS device with deep drain region TR Efland, S Pendharkar, DM Mosher, PC Mei US Patent 6,211,552, 2001 | 74 | 2001 |
| 7 to 30V state-of-art power device implementation in 0.25/spl mu/m LBC7 BiCMOS-DMOS process technology Pendharkar, Pan, Tamura, Todd, Efland 2004 Proceedings of the 16th International Symposium on Power Semiconductor …, 2004 | 73 | 2004 |
| Drain-extended MOS transistors with diode clamp and methods for making the same S Pendharkar US Patent 7,187,033, 2007 | 70 | 2007 |
| Lateral thinking about power devices (LDMOS) TR Efland, CY Tsai, S Pendharkar International Electron Devices Meeting 1998. Technical Digest (Cat. No …, 1998 | 69 | 1998 |
| Current collapse in GaN heterojunction field effect transistors for high-voltage switching applications J Joh, N Tipirneni, S Pendharkar, S Krishnan 2014 IEEE International Reliability Physics Symposium, 6C. 5.1-6C. 5.4, 2014 | 68 | 2014 |
| Short and long-term safe operating area considerations in LDMOS transistors PL Hower, S Pendharkar 2005 IEEE International Reliability Physics Symposium, 2005. Proceedings …, 2005 | 67 | 2005 |
| Zero voltage switching behavior of punchthrough and nonpunchthrough insulated gate bipolar transistors (IGBT's) S Pendharkar, K Shenai IEEE Transactions on Electron Devices 45 (8), 1826-1835, 1998 | 67 | 1998 |
| SCR-LDMOS. A novel LDMOS device with ESD robustness S Pendharkar, R Teggatz, J Devore, J Carpenter, T Efland, CY Tsai 12th International Symposium on Power Semiconductor Devices & ICs …, 2000 | 64 | 2000 |
| Method of manufacturing high side and low side guard rings for lowest parasitic performance in an H-bridge configuration S Pendharkar, TR Efland US Patent 6,395,593, 2002 | 54 | 2002 |
| Application reliability validation of GaN power devices SR Bahl, J Joh, L Fu, A Sasikumar, T Chatterjee, S Pendharkar 2016 IEEE International Electron Devices Meeting (IEDM), 20.5. 1-20.5. 4, 2016 | 52 | 2016 |
| Physics-based analytical model for HCS degradation in STI-LDMOS transistors S Reggiani, S Poli, M Denison, E Gnani, A Gnudi, G Baccarani, ... IEEE transactions on electron devices 58 (9), 3072-3080, 2011 | 52 | 2011 |
| Robust DEMOS transistors and method for making the same S Pendharkar, R Ramani, TR Efland US Patent 7,238,986, 2007 | 50 | 2007 |
| Buried floating layer structure for improved breakdown SP Pendharkar, B Hu, X Chen US Patent 8,264,038, 2012 | 49 | 2012 |
| Lateral double diffused metal oxide semiconductor device T Efland, CY Tsai, S Pendharkar US Patent 6,441,431, 2002 | 49 | 2002 |
| Electrothermal simulations in punchthrough and nonpunchthrough IGBT's S Pendharkar, M Trivedi, K Shenai IEEE transactions on electron devices 45 (10), 2222-2231, 1998 | 49 | 1998 |
