| PVT-Aware Design of Dopingless Dynamically Configurable Tunnel FET A Lahgere, C Sahu, J Singh IEEE Transactions on Electron Devices, 2015 | 68 | 2015 |
| Electrically doped dynamically configurable field-effect transistor for low-power and high-performance applications A Lahgere, C Sahu, J Singh Electronics Letter, 2015 | 44 | 2015 |
| Dopingless ferroelectric tunnel FET architecture for the improvement of performance of dopingless n-channel tunnel FETs A Lahgere, M Panchore, J Singh Superlattices and Microstructures 96, 16-25, 2016 | 37 | 2016 |
| 1-T capacitorless DRAM using bandgap-engineered silicon-germanium bipolar I-MOS A Lahgere, MJ Kumar IEEE Transactions on Electron Devices 64 (4), 1583-1590, 2017 | 27 | 2017 |
| The charge plasma npn impact ionization MOS on FDSOI technology: Proposal and analysis A Lahgere, MJ Kumar IEEE Transactions on Electron Devices 64 (1), 3-7, 2016 | 21 | 2016 |
| A tunnel dielectric-based junctionless transistor with reduced parasitic BJT action A Lahgere, MJ Kumar IEEE Transactions on Electron Devices 64 (8), 3470-3475, 2017 | 19 | 2017 |
| Evaluation of Radiation Resiliency on Emerging Junctionless/Dopingless Devices and Circuits N Kamal, A Lahgere, J Singh IEEE Transactions on Device Materials and Reliability 19 (4), 728-732, 2019 | 12 | 2019 |
| 1-T Capacitorless DRAM using Laterally Bandgap Engineered Si-Si: C Heterostructure Bipolar I-MOS for Improved Sensing Margin and Retention Time A Lahgere, MJ Kumar IEEE Transactions on Nanotechnology 17 (3), 543 - 551, 2018 | 9 | 2018 |
| A dynamically configurable silicon nanowire field effect transistor based on electrically doped source/drain C Sahu, A Lahgere, J Singh arXiv preprint arXiv:1412.4975, 2014 | 5 | 2014 |
| Design of leaky integrate and fire neuron for spiking neural networks using trench bipolar I-MOS A Lahgere IEEE Transactions on Nanotechnology, 2023 | 4 | 2023 |
| Ultra-low power reconfigurable synaptic and neuronal transistor for spiking neural network N Kamal, J Singh, A Lahgere, PK Tiwari IEEE Transactions on Nanotechnology, 2023 | 1 | 2023 |
| A Simulation Study of Bipolar I-MOS for ESD Protection A Lahgere, DS Gupta IEEE Transactions on Electron Devices, 2023 | | 2023 |
| Gate Grounded Trench I-MOS as an ESD Clamp for Sub-2V Applications A Lahgere, DS Gupta IEEE Access, 2023 | | 2023 |
| Transistor with phase transition material region between channel region and each source/drain region A Lahgere, PP Manik, P Javorka, A Icel, M Bajaj US Patent 11,387,364, 2022 | | 2022 |
| Doping-free tunnelling transistors–technology and modelling C Sahu, A Lahgere Advanced Technologies for Next Generation Integrated Circuits, 213, 2020 | | 2020 |
Jawar Singh, Ph.D.Professor, Electrical Engineering Department, Indian Institute of Technology PatnaVerified email at iitp.ac.in
