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Kwanyeob Chae
Kwanyeob Chae
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Title
Cited by
Cited by
Year
A dynamic timing error prevention technique in pipelines with time borrowing and clock stretching
K Chae, S Mukhopadhyay
IEEE Transactions on Circuits and Systems I: Regular Papers 61 (1), 74-83, 2013
322013
High-level system modeling and architecture exploration with systemc on a network SoC: S3C2510 case study
HO Jang, M Kang, M Lee, K Chae, K Lee, K Shim
Proceedings Design, Automation and Test in Europe Conference and Exhibition …, 2004
312004
A dynamic timing control technique utilizing time borrowing and clock stretching
K Chae, S Mukhopadhyay, CH Lee, J Laskar
IEEE Custom Integrated Circuits Conference 2010, 1-4, 2010
292010
All-digital adaptive clocking to tolerate transient supply noise in a low-voltage operation
K Chae, S Mukhopadhyay
IEEE Transactions on Circuits and Systems II: Express Briefs 59 (12), 893-897, 2012
252012
Advanced microcontroller bus architecture (amba) system with reduced power consumption and method of driving amba system
K Chae
US Patent 7,234,011, 2007
202007
Timing error prevention using elastic clocking
K Chae, CH Lee, S Mukhopadhyay
2011 IEEE International Conference on IC Design & Technology, 1-4, 2011
182011
Delay cells and delay line circuits having the same
K Chae
US Patent 7,486,125, 2009
162009
Analysis of the performance, power, and noise characteristics of a cmos image sensor with 3-d integrated image compression unit
D Lie, K Chae, S Mukhopadhyay
IEEE Transactions on Components, Packaging and Manufacturing Technology 4 (2 …, 2014
152014
Characterization of inverse temperature dependence in logic circuits
M Cho, M Khellah, K Chae, K Ahmed, J Tschanz, S Mukhopadhyay
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 1-4, 2012
152012
Tier adaptive body biasing: a post-silicon tuning method to minimize clock skew variations in 3-D ICs
K Chae, X Zhao, SK Lim, S Mukhopadhyay
IEEE Transactions on Components, Packaging and Manufacturing Technology 3 …, 2013
122013
Tier-adaptive-voltage-scaling (TAVS): A methodology for post-silicon tuning of 3D ICs
K Chae, S Mukhopadhyay
17th Asia and South Pacific Design Automation Conference, 277-282, 2012
122012
Adjustable delay cells and delay lines including the same
K Chae
US Patent 7,394,300, 2008
122008
Scan flip-flop circuit with reduced power consumption
K Chae
US Patent 7,231,569, 2007
112007
23.6 A 0.6 V 4.266 Gb/s/pin LPDDR4X interface with auto-DQS cleaning and write-VWM training for memory controller
SM Lee, J Oh, J Choi, S Ko, D Kim, K Koo, J Choi, Y Nam, S Park, H Lee, ...
2017 IEEE International Solid-State Circuits Conference (ISSCC), 398-399, 2017
102017
Memory controller with a self-test function, and method of testing a memory controller
K Chae
US Patent 7,657,803, 2010
102010
Integrated circuit devices having dual data rate (DDR) output circuits therein
K Chae
US Patent 7,447,110, 2008
102008
Parameter generating circuit for deciding priority of master blocks and method of generating parameter
K Chae
US Patent 7,028,121, 2006
102006
A low power 8-tap digital FIR filter for PRML read channels
HJ Ki, CS Lee, WH Paik, IC Hwang, KY Chae, JS Yoo, SW Kim
International journal of electronics 87 (4), 445-455, 2000
102000
Double precharge TSPC for high-speed dual-modulus prescaler
KY Chae, HJ Ki, IC Hwang, SW Kim
ICVC'99. 6th International Conference on VLSI and CAD (Cat. No. 99EX361 …, 1999
101999
Resilient pipeline under supply noise with programmable time borrowing and delayed clock gating
K Chae, S Mukhopadhyay
IEEE Transactions on Circuits and Systems II: Express Briefs 61 (3), 173-177, 2014
92014
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