Kaushik De
Kaushik De
Synopsys Scientist at Synopsys
Verified email at synopsys.com - Homepage
Title
Cited by
Cited by
Year
RSYN: A system for automated synthesis of reliable multilevel circuits
K De, C Natarajan, D Nair, P Banerjee
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2 (2), 186-195, 1994
1441994
Synthesis of delay fault testable combinational logic
K Roy, JA Abraham, K De, S Lusky
1989 IEEE International Conference on Computer-Aided Design, 418-421, 1989
791989
Defect isolation using scan-path testing and electron beam probing in multi-level high density asics
GA Lindberg, S Prasad, K De, AK Gunda
US Patent 5,663,967, 1997
621997
Failure analysis for full-scan circuits
K De, A Gunda
Proceedings of 1995 IEEE International Test Conference (ITC), 636-645, 1995
611995
System and method for representing a system level RTL design using HDL independent objects and translation to synthesizable RTL code
A Balakrishnan, K De, J Qian
US Patent 6,135,647, 2000
602000
Evaluation of early failure screening methods [ASICs]
T Barrette, V Bhide, K De, M Stover, E Sugasawara
Digest of Papers 1996 IEEE International Workshop on IDDQ Testing, 14-17, 1996
471996
Evaluation of early failure screening methods [ASICs]
T Barrette, V Bhide, K De, M Stover, E Sugasawara
Digest of Papers 1996 IEEE International Workshop on IDDQ Testing, 14-17, 1996
471996
Test methodology for embedded cores which protects intellectual property
K De
Proceedings. 15th IEEE VLSI Test Symposium (Cat. No. 97TB100125), 2-9, 1997
321997
Accurate pre-layout estimation of standard cell characteristics
H Yoshida, K De, V Boppana
Proceedings of the 41st annual Design Automation Conference, 208-211, 2004
242004
ProperSYN: A portable parallel algorithm for logic synthesis
K De, B Ramkumar, P Banerjee
Proceedings of the 1992 IEEE/ACM international conference on Computer-aided …, 1992
221992
Parallel algorithms for logic synthesis using the MIS approach
K De, LA Chandy, S Roy, S Parkes, P Banerjee
Proceedings of 9th International Parallel Processing Symposium, 579-585, 1995
191995
Parallel algorithms for logic synthesis using the MIS approach
K De, LA Chandy, S Roy, S Parkes, P Banerjee
Proceedings of 9th International Parallel Processing Symposium, 579-585, 1995
191995
Test shells for protecting proprietary information in asic cores
K De, S Venkatraman, A Gunda
US Patent 5,903,578, 1999
181999
Protecting proprietary asic design information using boundary scan on selective inputs and outputs
K De
US Patent 5,638,380, 1997
181997
Logic partitioning and resynthesis for testability
K De, P Banerjee
1991, Proceedings. International Test Conference, 906, 1991
171991
Method and apparatus for extracting assume properties from a constrained random test-bench
K De, E Cerny, P Dasgupta, B Pal, PP Chakrabarti
US Patent 7,797,123, 2010
142010
Method and apparatus for extracting assume properties from a constrained random test-bench
K De, E Cerny, P Dasgupta, B Pal, PP Chakrabarti
US Patent 7,797,123, 2010
142010
PREST: a system for logic partitioning and resynthesis for testability
K De, P Banerjee
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 1 (4), 514-525, 1993
111993
PREST: a system for logic partitioning and resynthesis for testability
K De, P Banerjee
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on 1 (4), 514-525, 1993
111993
Reliability driven logic synthesis of multilevel circuits
K De, C Wu, P Banerjee
Circuits and Systems, 1992. ISCAS'92. Proceedings., 1992 IEEE International …, 1992
111992
The system can't perform the operation now. Try again later.
Articles 1–20