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Hiroki Nakahara
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BRein memory: A single-chip binary/ternary reconfigurable in-memory deep neural network accelerator achieving 1.4 TOPS at 0.6 W
K Ando, K Ueyoshi, K Orimo, H Yonekawa, S Sato, H Nakahara, ...
IEEE Journal of Solid-State Circuits 53 (4), 983-994, 2017
1162017
A lightweight YOLOv2: A binarized CNN with a parallel support vector regression for an FPGA
H Nakahara, H Yonekawa, T Fujii, S Sato
Proceedings of the 2018 ACM/SIGDA International Symposium on field …, 2018
1052018
A fully connected layer elimination for a binarizec convolutional neural network on an FPGA
H Nakahara, T Fujii, S Sato
2017 27th international conference on field programmable logic and …, 2017
882017
BRein memory: A 13-layer 4.2 K neuron/0.8 M synapse binary/ternary reconfigurable in-memory deep neural network accelerator in 65 nm CMOS
K Ando, K Ueyoshi, K Orimo, H Yonekawa, S Sato, H Nakahara, M Ikebe, ...
2017 Symposium on VLSI Circuits, C24-C25, 2017
792017
On-chip memory based binarized convolutional deep neural network applying batch normalization free technique on an FPGA
H Yonekawa, H Nakahara
2017 IEEE International Parallel and Distributed Processing Symposium …, 2017
792017
A deep convolutional neural network based on nested residue number system
H Nakahara, T Sasao
2015 25th International Conference on Field Programmable Logic and …, 2015
652015
A memory-based realization of a binarized deep convolutional neural network
H Nakahara, H Yonekawa, T Sasao, H Iwamoto, M Motomura
2016 International Conference on Field-Programmable Technology (FPT), 277-280, 2016
332016
A regular expression matching circuit based on a decomposed automaton
H Nakahara, T Sasao, M Matsuura
International Symposium on Applied Reconfigurable Computing, 16-28, 2011
312011
A High-speed Low-power Deep Neural Network on an FPGA based on the Nested RNS: Applied to an Object Detector
H Nakahara, T Sasao
2018 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2018
282018
An object detector based on multiscale sliding window search using a fully pipelined binarized CNN on an FPGA
H Nakahara, H Yonekawa, S Sato
2017 international conference on field programmable technology (ICFPT), 168-175, 2017
262017
A random forest using a multi-valued decision diagram on an FPGA
H Nakahara, A Jinguji, S Sato, T Sasao
2017 IEEE 47th international symposium on multiple-valued logic (ISMVL), 266-271, 2017
242017
High-throughput convolutional neural network on an fpga by customized jpeg compression
H Nakahara, Z Que, W Luk
2020 IEEE 28th Annual International Symposium on Field-Programmable Custom …, 2020
232020
A regular expression matching circuit based on a modular non-deterministic finite automaton with multi-character transition
H Nakahara, T Sasao, M Matsuura
Proc. 16th Workshop on Synthesis And System Integration of Mixed Information …, 2010
212010
New generation dynamically reconfigurable processor technology for accelerating embedded AI applications
T Fujii, T Toi, T Tanaka, K Togawa, T Kitaoka, K Nishino, N Nakamura, ...
2018 IEEE Symposium on VLSI Circuits, 41-42, 2018
202018
An FPGA realization of a deep convolutional neural network using a threshold neuron pruning
T Fujii, S Sato, H Nakahara, M Motomura
International Symposium on Applied Reconfigurable Computing, 268-280, 2017
182017
A realization of index generation functions using modules of uniform sizes
T Sasao, M Matsuura, H Nakahara
19th International Workshop on Logic and Synthesis (IWLS-2010), 201-208, 2010
172010
A comparison of architectures for various decision diagram machines
H Nakahara, T Sasao, M Matsuura
2010 40th IEEE International Symposium on Multiple-Valued Logic, 229-234, 2010
172010
The parallel sieve method for a virus scanning engine
H Nakahara, T Sasao, M Matsuura, Y Kawamura
2009 12th Euromicro Conference on Digital System Design, Architectures …, 2009
172009
A CAM emulator using look-up table cascades
H Nakahara, T Sasao, M Matsuura
2007 IEEE International Parallel and Distributed Processing Symposium, 1-8, 2007
172007
Realization of sequential circuits by look-up table rings
T Sasao, H Nakahara, M Matsuura, Y Iguchi
The 2004 47th Midwest Symposium on Circuits and Systems, 2004. MWSCAS'04. 1 …, 2004
172004
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Articles 1–20