| BRein memory: A single-chip binary/ternary reconfigurable in-memory deep neural network accelerator achieving 1.4 TOPS at 0.6 W K Ando, K Ueyoshi, K Orimo, H Yonekawa, S Sato, H Nakahara, ... IEEE Journal of Solid-State Circuits 53 (4), 983-994, 2017 | 187 | 2017 |
| A lightweight YOLOv2: A binarized CNN with a parallel support vector regression for an FPGA H Nakahara, H Yonekawa, T Fujii, S Sato Proceedings of the 2018 ACM/SIGDA International Symposium on field …, 2018 | 170 | 2018 |
| A fully connected layer elimination for a binarizec convolutional neural network on an FPGA H Nakahara, T Fujii, S Sato 2017 27th international conference on field programmable logic and …, 2017 | 128 | 2017 |
| On-chip memory based binarized convolutional deep neural network applying batch normalization free technique on an FPGA H Yonekawa, H Nakahara 2017 IEEE international parallel and distributed processing symposium …, 2017 | 111 | 2017 |
| BRein memory: A 13-layer 4.2 K neuron/0.8 M synapse binary/ternary reconfigurable in-memory deep neural network accelerator in 65 nm CMOS K Ando, K Ueyoshi, K Orimo, H Yonekawa, S Sato, H Nakahara, M Ikebe, ... 2017 Symposium on VLSI Circuits, C24-C25, 2017 | 97 | 2017 |
| A deep convolutional neural network based on nested residue number system H Nakahara, T Sasao 2015 25th International Conference on Field Programmable Logic and …, 2015 | 83 | 2015 |
| Principles and structures of FPGAs H Amano | 71 | 2018 |
| A memory-based realization of a binarized deep convolutional neural network H Nakahara, H Yonekawa, T Sasao, H Iwamoto, M Motomura 2016 International Conference on Field-Programmable Technology (FPT), 277-280, 2016 | 55 | 2016 |
| A random forest using a multi-valued decision diagram on an FPGA H Nakahara, A Jinguji, S Sato, T Sasao 2017 IEEE 47th international symposium on multiple-valued logic (ISMVL), 266-271, 2017 | 47 | 2017 |
| A High-speed Low-power Deep Neural Network on an FPGA based on the Nested RNS: Applied to an Object Detector H Nakahara, T Sasao 2018 IEEE international symposium on circuits and systems (ISCAS), 1-5, 2018 | 40 | 2018 |
| High-throughput convolutional neural network on an FPGA by customized JPEG compression H Nakahara, Z Que, W Luk 2020 IEEE 28th Annual International Symposium on Field-Programmable Custom …, 2020 | 38 | 2020 |
| An object detector based on multiscale sliding window search using a fully pipelined binarized CNN on an FPGA H Nakahara, H Yonekawa, S Sato 2017 international conference on field programmable technology (ICFPT), 168-175, 2017 | 38 | 2017 |
| A regular expression matching circuit based on a decomposed automaton H Nakahara, T Sasao, M Matsuura Reconfigurable Computing: Architectures, Tools and Applications: 7th …, 2011 | 37 | 2011 |
| Optimizing reconfigurable recurrent neural networks Z Que, H Nakahara, E Nurvitadhi, H Fan, C Zeng, J Meng, X Niu, W Luk 2020 IEEE 28th Annual International Symposium on Field-Programmable Custom …, 2020 | 32 | 2020 |
| New generation dynamically reconfigurable processor technology for accelerating embedded AI applications T Fujii, T Toi, T Tanaka, K Togawa, T Kitaoka, K Nishino, N Nakamura, ... 2018 IEEE symposium on VLSI circuits, 41-42, 2018 | 31 | 2018 |
| FPGA-based training accelerator utilizing sparseness of convolutional neural network H Nakahara, Y Sada, M Shimoda, K Sayama, A Jinguji, S Sato 2019 29th International Conference on Field Programmable Logic and …, 2019 | 28 | 2019 |
| All binarized convolutional neural network and its implementation on an FPGA M Shimoda, S Sato, H Nakahara 2017 International Conference on Field Programmable Technology (ICFPT), 291-294, 2017 | 28 | 2017 |
| A demonstration of FPGA-based you only look once version2 (YOLOv2) H Nakahara, M Shimoda, S Sato 2018 28th International Conference on Field Programmable Logic and …, 2018 | 26 | 2018 |
| A regular expression matching circuit based on a modular non-deterministic finite automaton with multi-character transition H Nakahara, T Sasao, M Matsuura Proc. 16th Workshop on Synthesis And System Integration of Mixed Information …, 2010 | 24 | 2010 |
| An FPGA-based low-latency accelerator for randomly wired neural networks R Kuramochi, H Nakahara 2020 30th International Conference on Field-Programmable Logic and …, 2020 | 22 | 2020 |
Shimpei SatoShinshu UniversityVerified email at shinshu-u.ac.jp
