| Control device for a system-on-chip and corresponding method D Mangano, G Falconeri, G Strani US Patent 8,412,795, 2013 | 48 | 2013 |
| Closed loop end-to-end qos on-chip architecture IA Urzi, N Graciannette, D Mangano US Patent App. 14/059,252, 2014 | 41 | 2014 |
| GALS networks on chip: a new solution for asynchronous delay-insensitive links G Campobello, M Castano, C Ciofi, D Mangano Proceedings of the Design Automation & Test in Europe Conference 2, 1-6, 2006 | 38 | 2006 |
| Skew insensitive physical links for network on chip D Mangano, R Locatelli, A Scandurra, C Pistritto, M Coppola, L Fanucci, ... 2006 1st International Conference on Nano-Networks and Workshops, 1-5, 2006 | 31 | 2006 |
| A nuca model for embedded systems cache design P Foglia, D Mangano, CA Prete 3rd Workshop on Embedded Systems for Real-Time Multimedia, 2005., 41-46, 2005 | 26 | 2005 |
| System for interfacing an LC sensor, related method and computer program product D Mangano, R Condorelli US Patent 10,168,443, 2019 | 18 | 2019 |
| Method and systems for mesochronous communications in multiple clock domains and corresponding computer program product D Mangano, G Guarnaccia, C Pistritto US Patent 7,925,803, 2011 | 17 | 2011 |
| Circuit for asynchronous communications, related system and method D Mangano, S Pisasale, C Pistritto US Patent 9,191,033, 2015 | 15 | 2015 |
| Transaction reordering system and method with protocol indifference D Mangano, IA Urzi US Patent 8,677,045, 2014 | 12 | 2014 |
| Interconnection method and device, for example for systems-on-chip D Mangano, IA Urzi US Patent 8,631,184, 2014 | 12 | 2014 |
| Method of exchanging information in a communication network, corresponding communication network and computer program product A Scandurra, G Falconeri, D Mangano US Patent 8,199,751, 2012 | 12 | 2012 |
| Communication interface for interfacing a transmission circuit with an interconnection network, and corresponding system and integrated circuit D Mangano, M Dondini, S Pisasale US Patent 9,959,226, 2018 | 11 | 2018 |
| Communication system for interfacing a plurality of transmission circuits with an interconnection network, and corresponding integrated circuit M Dondini, D Mangano, G Falconeri US Patent 9,471,521, 2016 | 11 | 2016 |
| System for designing network on chip interconnect arrangements D Mangano, IA Urzi US Patent 9,202,002, 2015 | 11 | 2015 |
| System for the management of out-of-order traffic in an interconnect network and corresponding method and integrated circuit M Dondini, D Mangano US Patent 10,616,333, 2020 | 10 | 2020 |
| Method of handling transactions, corresponding system and computer program product D Mangano, IA Urzi US Patent 9,697,161, 2017 | 9 | 2017 |
| A cache design for high performance embedded systems P Foglia, D Mangano, CA Prete Journal of Embedded Computing 1 (4), 587-597, 2005 | 9 | 2005 |
| Interface system, and corresponding integrated circuit and method D Mangano, S Pisasale, IA Urzi US Patent 9,026,761, 2015 | 8 | 2015 |
| Method and device for managing queues, and corresponding computer program product D Mangano, G Strano, S Pisasale US Patent 8,688,872, 2014 | 6 | 2014 |
| Reordering arrangement IA Urzi, D Mangano US Patent App. 13/248,316, 2012 | 6 | 2012 |
Pierfrancesco FogliaUniversita di PisaVerified email at iet.unipi.it
