| Cell design methodology based on transmission gate for low-power high-speed balanced XOR-XNOR circuits in hybrid-CMOS logic style T Nikoubin, M Grailoo, SH Mozafari Journal of Low Power Electronics 6 (4), 503-512, 2010 | 34 | 2010 |
| PipeBERT: high-throughput BERT inference for arm big. Little multi-core processors HY Chang, SH Mozafari, C Chen, JJ Clark, BH Meyer, WJ Gross Journal of Signal Processing Systems 95 (7), 877-894, 2023 | 10 | 2023 |
| A Low Cost circuit level fault detection technique to Full Adder design SH Mozafari, M Fazeli, S Hessabi, SG Miremadi 2011 18th IEEE International Conference on Electronics, Circuits, and …, 2011 | 7 | 2011 |
| Hot spare components for performance-cost improvement in multi-core SIMT SH Mozafari, BH Meyer 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and …, 2015 | 6 | 2015 |
| Yield-aware performance-cost characterization for multi-core SIMT SH Mozafari, BH Meyer, K Skadron Proceedings of the 25th edition on great lakes symposium on VLSI, 237-240, 2015 | 6 | 2015 |
| Implementing convolutional neural networks using hartley stochastic computing with adaptive rate feature map compression SH Mozafari, JJ Clark, WJ Gross, BH Meyer IEEE Open Journal of Circuits and Systems 2, 805-819, 2021 | 4 | 2021 |
| Efficient performance evaluation of multi-core simt processors with hot redundancy SH Mozafari, BH Meyer IEEE Transactions on Emerging Topics in Computing 6 (4), 498-510, 2016 | 4 | 2016 |
| Hartley stochastic computing for convolutional neural networks SH Mozafari, JJ Clark, WJ Gross, BH Meyer 2021 IEEE Workshop on Signal Processing Systems (SiPS), 1-6, 2021 | 3 | 2021 |
| Hot sparing for lifetime-chip-performance and cost improvement in application specific SIMT processors SH Mozafari, BH Meyer Design Automation for Embedded Systems 24, 249-266, 2020 | 3 | 2020 |
| Characterizing the effectiveness of hot sparing on cost and performance-per-watt in application specific SIMT SH Mozafari, BH Meyer Integration 69, 198-209, 2019 | 3 | 2019 |
| Fast heterogeneous task mapping for reducing edge dnn latency ML Kornelsen, SH Mozafari, JJ Clark, BH Meyer, WJ Gross 2022 IEEE 33rd International Conference on Application-specific Systems …, 2022 | 2 | 2022 |
| Constructing new matrices and investigating their determinants N Mirashe, AR Moghaddamfar, SH Mozafari, SMH Pooya, S Navid Salehy, ... Asian-European Journal of Mathematics 1 (04), 575-588, 2008 | 2 | 2008 |
| BERTPerf: Inference Latency Predictor for BERT on ARM big. LITTLE Multi-Core Processors M Abdelgawad, SH Mozafari, JJ Clark, BH Meyer, WJ Gross 2022 IEEE Workshop on Signal Processing Systems (SiPS), 1-6, 2022 | 1 | 2022 |
| Work-in-progress: Utilizing latency and accuracy predictors for efficient hardware-aware NAS N Firouzian, SH Mozafari, JJ Clark, WJ Gross, BH Meyer 2022 International Conference on Hardware/Software Codesign and System …, 2022 | 1 | 2022 |
| Area, throughput, and power trade-offs for FPGA-and ASIC-based execution stream compression MI Mera, J Caplan, SH Mozafari, BH Meyer, P Milder ACM Transactions on Embedded Computing Systems (TECS) 16 (4), 1-20, 2017 | 1 | 2017 |
| The determinants of matrices constructed by subdiagonal, main diagonal and superdiagonal N Mirashe, AR Moghaddamfar, SH Mozafari Lobachevskii Journal of Mathematics 31 (3), 295-306, 2010 | 1 | 2010 |
| Automatic Pruning of Fine-tuning Datasets for Transformer-based Language Models M Tayaranian, SH Mozafari, BH Meyer, JJ Clark, WJ Gross arXiv preprint arXiv:2407.08887, 2024 | | 2024 |
| Faster Inference of Integer SWIN Transformer by Removing the GELU Activation M Tayaranian, SH Mozafari, JJ Clark, B Meyer, W Gross arXiv preprint arXiv:2402.01169, 2024 | | 2024 |
| Efficient 1D Grouped Convolution for PyTorch a Case Study: Fast On-Device Fine-Tuning for SqueezeBERT SH Mozafari, JJ Clark, WJ Gross, BH Meyer 2023 IEEE 34th International Conference on Application-specific Systems …, 2023 | | 2023 |
| High-Throughput Edge Inference for BERT Models via Neural Architecture Search and Pipeline HY Chang, SH Mozafari, JJ Clark, BH Meyer, WJ Gross Proceedings of the Great Lakes Symposium on VLSI 2023, 455-459, 2023 | | 2023 |
Brett H MeyerAssociate Professor of ECE, McGill UniversityVerified email at mcgill.ca
