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Venkatesh (P.G.) Gopinath
Venkatesh (P.G.) Gopinath
Adesto Technologies
Verified email at adestotech.com
Title
Cited by
Cited by
Year
On the plasma parameters of a planar inductive oxygen discharge
JT Gudmundsson, AM Marakhtanov, KK Patel, VP Gopinath, ...
Journal of Physics D: Applied Physics 33 (11), 1323, 2000
1192000
Multipactor electron discharge physics using an improved secondary emission model
VP Gopinath, JP Verboncoeur, CK Birdsall
Physics of Plasmas 5 (5), 1535-1540, 1998
981998
Conductive-bridge memory (CBRAM) with excellent high-temperature retention
JR Jameson, P Blanchard, C Cheng, J Dinh, A Gallo, V Gopalakrishnan, ...
2013 IEEE International Electron Devices Meeting, 30.1. 1-30.1. 4, 2013
812013
Resistive switching devices and methods of formation thereof
Gopalan, S Chakravarthy (Santa Clara, CA), G Jeffrey (Sunnyvale, CA), ...
US Patent 8,941,089, 2015
712015
Fabrication of trenches with multiple depths on the same substrate
MR Mirbedini, VP Gopinath, H Lin, V Hornback, D Defibaugh, Y Le
US Patent 6,864,152, 2005
562005
Three-dimensional electromagnetic PIC model of a compact ECR plasma source
VP Gopinath, TA Grotjohn
IEEE transactions on plasma science 23 (4), 602-608, 1995
331995
Voltage level shifter
PJ Wright, VP Gopinath, TA Randazzo
US Patent 6,614,283, 2003
312003
Similarity of stability characteristics of planar and coaxial crossed‐field diodes
VP Gopinath, JP Verboncoeur, CK Birdsall
Physics of Plasmas 3 (7), 2766-2769, 1996
241996
Conductive bridging RAM (CBRAM): then, now, and tomorrow
JR Jameson, P Blanchard, J Dinh, N Gonzales, V Gopalakrishnan, ...
ECS Transactions 75 (5), 41, 2016
232016
STI stress-induced increase in reverse bias junction capacitance
VP Gopinath, H Puchner, M Mirabedini
IEEE Electron Device Letters 23 (6), 312-314, 2002
232002
Method of automatically detecting offside in Soccer using fixed and wireless sensors and central server
VP Gopinath, J Gopinath
US Patent App. 12/131,086, 2009
212009
Vertical double gate Z-RAM technology with remarkable low voltage operation for DRAM application
JS Kim, SW Chung, TS Jang, SH Lee, DH Son, SJ Chung, SM Hwang, ...
2010 Symposium on VLSI Technology, 163-164, 2010
152010
Modeling the electromagnetic excitation of a compact ECR ion/free radical sourcea)
TA Grotjohn, W Tan, V Gopinath, AK Srivastava, J Asmussen
Review of scientific instruments 65 (5), 1761-1765, 1994
151994
Resistive switching devices having a switching layer and an intermediate electrode layer and methods of formation thereof
JR Jameson III, JE Sanchez, WT Lee, FS Koushan
US Patent 9,252,359, 2016
142016
Towards automotive grade embedded RRAM
JR Jameson, J Dinh, N Gonzales, S Hollmer, S Hsu, D Kim, F Koushan, ...
2018 48th European Solid-State Device Research Conference (ESSDERC), 58-61, 2018
122018
Process for improving mechanical strength of layers of low k dielectric material
CE May, VP Gopinath, PJ Wright
US Patent 6,566,244, 2003
112003
Shallow trench isolation structure with low trench parasitic capacitance
VP Gopinath, A Kamath, MR Mirabedini, MY Lee
US Patent 7,619,294, 2009
102009
Shallow trench isolation structure for laser thermal processing
H Puchner, VP Gopinath
US Patent 6,734,081, 2004
102004
Leakage power optimization considering gate input activity and timing slack
VP Gopinath, K Sundaresan, J Oh, K Peng, RE Mains
US Patent 7,802,217, 2010
82010
Polysilicon gate salicidation
V Gopinath, M Mirabedini, CE May, A Kamath
US Patent 6,544,829, 2003
82003
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