| First Vertically Stacked Tensily Strained Ge 0.98 Si 0.02 nGAAFETs with No Parasitic Channel and L G= 40 nm Featuring Record I ON= 48 μA at V OV= V DS= 0.5 V and Record G m … CT Tu, YS Huang, FL Lu, HH Liu, CY Lin, YC Liu, CW Liu 2019 IEEE International Electron Devices Meeting (IEDM), 29.3. 1-29.3. 4, 2019 | 15 | 2019 |
| Energy-efficient in-memory address calculation A Yousefzadeh, J Stuijt, M Hijdra, HH Liu, A Gebregiorgis, A Singh, ... ACM Transactions on Architecture and Code Optimization (TACO) 19 (4), 1-16, 2022 | 5 | 2022 |
| Extended methodology to determine SRAM write margin in resistance-dominated technology node HH Liu, SM Salahuddin, D Abdi, R Chen, P Weckx, P Matagne, F Catthoor IEEE Transactions on Electron Devices 69 (6), 3113-3117, 2022 | 5 | 2022 |
| CFET SRAM DTCO, Interconnect Guideline, and Benchmark for CMOS Scaling HH Liu, SM Salahuddin, BT Chan, P Schuddinck, Y Xiang, G Hellings, ... IEEE Transactions on Electron Devices 70 (3), 883-890, 2023 | 4 | 2023 |
| Design-technology co-optimization overview of CFET architecture G Mirabelli, P Schuddinck, HH Liu, S Yang, O Zografos, SM Salahuddin, ... DTCO and Computational Patterning II 12495, 117-123, 2023 | 3 | 2023 |
| DTCO of sequential and monolithic CFET SRAM HH Liu, SM Salahuddin, BT Chan, P Schuddinck, Y Xiang, P Weckx, ... DTCO and Computational Patterning II 12495, 219-225, 2023 | 3 | 2023 |
| Graphene-Based Interconnect Exploration for Large SRAM Caches for Ultrascaled Technology Nodes Z Pei, M Mayahinia, HH Liu, M Tahoori, F Catthoor, Z Tokei, C Pan IEEE Transactions on Electron Devices 70 (1), 230-238, 2022 | 3 | 2022 |
| Different infrared responses from the stacked channels and parasitic channel of stacked GeSn channel transistors HH Liu, YS Huang, FL Lu, HY Ye, CW Liu IEEE Electron Device Letters 41 (1), 147-150, 2019 | 3 | 2019 |
| Optical Detection of Parasitic Channels of Vertically Stacked Ge0.98Si0.02 nGAAFETs SY Lin, HH Liu, CT Tu, YS Huang, FL Lu, CW Liu IEEE Transactions on Electron Devices 67 (10), 4073-4078, 2020 | 2 | 2020 |
| Ultimate MRAM Scaling: Design Exploration of High-Density, High-Performance and Energy-Efficient VGSOT for Last Level Cache M Gupta, Y Xiangt, F García-Redondo, K Cai, D Abdi, HH Liu, S Rao, ... 2023 International Electron Devices Meeting (IEDM), 1-4, 2023 | 1 | 2023 |
| Technology/Memory Co-Design and Co-Optimization Using E-Tree Interconnect Z Pei, M Mayahinia, HH Liu, M Tahoori, F Catthoor, Z Tokei, C Pan Proceedings of the Great Lakes Symposium on VLSI 2023, 159-162, 2023 | 1 | 2023 |
| Emerging Interconnect Exploration for SRAM Application Using Nonconventional H-Tree and Center-Pin Access Z Pei, M Mayahinia, HH Liu, M Tahoori, SM Salahuddin, F Catthoor, ... 2023 24th International Symposium on Quality Electronic Design (ISQED), 1-1, 2023 | 1 | 2023 |
| Bit Cell with Isolating Wall HH Liu, SM Salahuddin, BT Chan US Patent App. 18/335,320, 2023 | | 2023 |
| Bit Cell for Static Random Access Memory HH Liu, SM Salahuddin, BT Chan US Patent App. 18/335,310, 2023 | | 2023 |
| CFET SRAM With Double-Sided Interconnect Design and DTCO Benchmark HH Liu, P Schuddinck, Z Pei, L Verschueren, H Mertens, SM Salahuddin, ... IEEE Transactions on Electron Devices, 2023 | | 2023 |
| Electromigration-aware design technology co-optimization for SRAM in advanced technology nodes M Mayahinia, HH Liu, S Mishra, Z Tokei, F Catthoor, M Tahoori 2023 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-6, 2023 | | 2023 |
| Infrared Response of Stacked GeSn Transistors HH Liu, YS Huang, FL Lu, HY Ye, CW Liu 2020 International Symposium on VLSI Technology, Systems and Applications …, 2020 | | 2020 |
