Taniya Siddiqua
Taniya Siddiqua
Component Design Engineer, Intel Corporation, Hudson, MA
Verified email at cs.virginia.edu
Title
Cited by
Cited by
Year
How I Learned to Stop Worrying and Love Flash Endurance.
V Mohan, T Siddiqua, S Gurumurthi, MR Stan
HotStorage 10, 3-3, 2010
712010
Cost-effective design of scalable high-performance systems using active and passive interposers
D Stow, Y Xie, T Siddiqua, GH Loh
2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 728-735, 2017
462017
Recovery boosting: A technique to enhance NBTI recovery in SRAM arrays
T Siddiqua, S Gurumurthi
2010 IEEE Computer Society Annual Symposium on VLSI, 393-398, 2010
442010
A multi-level approach to reduce the impact of nbti on processor functional units
T Siddiqua, S Gurumurthi
Proceedings of the 20th symposium on Great lakes symposium on VLSI, 67-72, 2010
432010
Modeling and analyzing NBTI in the presence of process variation
T Siddiqua, S Gurumurthi, MR Stan
2011 12th International Symposium on Quality Electronic Design, 1-8, 2011
382011
Enhancing NBTI recovery in SRAM arrays through recovery boosting
T Siddiqua, S Gurumurthi
IEEE transactions on very large scale integration (VLSI) systems 20 (4), 616-629, 2011
362011
Analysis and modeling of memory errors from large-scale field data collection
T Siddiqua, AE Papathanasiou, A Biswas, S Gurumurthi
ser. SELSE 16, 17-18, 2013
292013
Balancing soft error coverage with lifetime reliability in redundantly multithreaded processors
T Siddiqua, S Gurumurthi
2009 IEEE International Symposium on Modeling, Analysis & Simulation of …, 2009
152009
Lessons learned from memory errors observed over the lifetime of Cielo
S Levy, KB Ferreira, N DeBardeleben, T Siddiqua, V Sridharan, ...
SC18: International Conference for High Performance Computing, Networking …, 2018
142018
Improving dram fault characterization through machine learning
E Baseman, N DeBardeleben, K Ferreira, S Levy, S Raasch, V Sridharan, ...
2016 46th Annual IEEE/IFIP International Conference on Dependable Systems …, 2016
112016
Lifetime memory reliability data from the field
T Siddiqua, V Sridharan, SE Raasch, N DeBardeleben, KB Ferreira, ...
2017 IEEE International Symposium on Defect and Fault Tolerance in VLSI and …, 2017
92017
Physics-informed machine learning for DRAM error modeling
E Baseman, N DeBardeleben, S Blanchard, J Moore, O Tkachenko, ...
2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and …, 2018
72018
Nbti-aware dynamic instruction scheduling
T Siddiqua, S Gurumurthi
Proceedings of the 5th Workshop on Silicon Errors in Logic-System Effects, 2009
62009
Automating dram fault mitigation by learning from experience
E Baseman, N DeBardeleben, K Ferreira, V Sridharan, T Siddiqua, ...
2017 47th Annual IEEE/IFIP International Conference on Dependable Systems …, 2017
32017
Elongate component supported by support component separate from circuit boards
R Richardson, W Scofield
US Patent App. 10/073,746, 2002
32002
Mutation Resistant Runtime Code using Kernel Attestation
K Chawla, T Siddiqua
22010
A Multi-Level Approach to NBTI Mitigation in Processors
T Siddiqua
PhD thesis, University of Virginia, 2012
12012
33rd IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems
M Ottavi, G Furano, M Psarakis, P Joshi, L Cassano, T Siddiqua
2020
Method and apparatus for providing distributed checkpointing
S Blagodurov, T Siddiqua, V Sridharan
US Patent 10,073,746, 2018
2018
Lessons Learned from Errors Observed over the Lifetime of Cielo.
SLN Levy, KB Ferreira, N Debardeleben, T Siddiqua, V Sridharan, ...
Sandia National Lab.(SNL-NM), Albuquerque, NM (United States), 2018
2018
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