Vassilis Paliouras
Vassilis Paliouras
Professor, Department of Electrical and Computer Engineering, University of Patras
Adresse e-mail validée de ece.upatras.gr - Page d'accueil
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Considering the alternatives in low-power design
T Stouraitis, V Paliouras
IEEE Circuits and Devices Magazine 17 (4), 22-29, 2001
1072001
Low-power properties of the logarithmic number system
V Paliouras, T Stouraitis
Proceedings 15th IEEE Symposium on Computer Arithmetic. ARITH-15 2001, 229-236, 2001
842001
Low-power logarithmic number system addition/subtraction and their impact on digital filters
I Kouretas, C Basetas, V Paliouras
IEEE transactions on computers 62 (11), 2196-2209, 2012
452012
A VLSI design methodology for RNS full adder-based inner product architectures
DJ Soudris, V Paliouras, T Stouraitis, CE Goutis
IEEE Transactions on Circuits and Systems II: Analog and Digital Signal …, 1997
391997
Multifunction architectures for RNS processors
V Paliouras, T Stouraitis
IEEE Transactions on Circuits and Systems II: Analog and Digital Signal …, 1999
371999
A novel algorithm for accurate logarithmic number system subtraction
V Paliouras, T Stouraitis
1996 IEEE International Symposium on Circuits and Systems. Circuits and …, 1996
341996
A low-complexity combinatorial RNS multiplier
V Paliouras, K Karagianni, T Stouraitis
IEEE Transactions on Circuits and Systems II: Analog and Digital Signal …, 2001
322001
A floating-point processor for fast and accurate sine/cosine evaluation
V Paliouras, K Karagianni, T Stouraitis
IEEE Transactions on Circuits and Systems II: Analog and Digital Signal …, 2000
322000
Logarithmic number system for low-power arithmetic
V Paliouras, T Stouraitis
International Workshop on Power and Timing Modeling, Optimization and …, 2000
312000
Novel high-radix residue number system architectures
V Paliouras, T Stouraitis
IEEE Transactions on Circuits and Systems II: Analog and Digital Signal …, 2000
292000
A low-complexity high-radix RNS multiplier
I Kouretas, V Paliouras
IEEE Transactions on Circuits and Systems I: Regular Papers 56 (11), 2449-2462, 2009
252009
A low-power termination criterion for iterative LDPC code decoders
G Glikiotis, V Paliouras
IEEE Workshop on Signal Processing Systems Design and Implementation, 2005 …, 2005
252005
Novel high-radix residue number system multipliers and adders
V Paliouras, T Stouraitis
ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits …, 1999
251999
LDPC encoding and decoding techniques
I Tsatsaragkos, A Mahdi, N Kanistras, V Paliouras
US Patent 8,739,001, 2014
222014
A flexible high-throughput hardware architecture for a gaussian noise generator
I Paraskevakos, V Paliouras
2011 IEEE International Conference on Acoustics, Speech and Signal …, 2011
212011
A novel architecture and a systematic graph-based optimization methodology for modulo multiplication
G Dimitrakopoulos, V Paliouras
IEEE Transactions on Circuits and Systems I: Regular Papers 51 (2), 354-370, 2004
192004
Residue arithmetic for variation-tolerant design of multiply-add units
I Kouretas, V Paliouras
International Workshop on Power and Timing Modeling, Optimization and …, 2009
182009
A low-complexity PTS-based PAPR reduction technique for OFDM signals without transmission of side information
T Giannopoulos, V Paliouras
Journal of signal processing systems 56 (2-3), 141-153, 2009
182009
Systematic derivation of the processing element of a systolic array based on residue number system
V Paliouras, D Soudris, T Stouraitis
[Proceedings] 1992 IEEE International Symposium on Circuits and Systems 2 …, 1992
171992
A reconfigurable LDPC decoder optimized for 802.11 n/ac applications
I Tsatsaragkos, V Paliouras
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 26 (1), 182-195, 2018
162018
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