| Template based synthesis for high performance computing M Fujita, Y Kimura, Q Wang 2017 IFIP/IEEE International Conference on Very Large Scale Integration …, 2017 | 8 | 2017 |
| Signal selection methods for efficient multi-target correction Y Kimura, AM Gharehbaghi, M Fujita 2019 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2019 | 7 | 2019 |
| Methods of equivalence checking and ECO support under C-based design through reproduction of C descriptions from implementation designs Q Wang, Y Kimura, M Fujita 2017 18th International Symposium on Quality Electronic Design (ISQED), 432-437, 2017 | 3 | 2017 |
| Synthesis and optimization of multiple portions of circuits for ECO based on set-covering and QBF formulations M Fujita, Y Kimura, X Le, Y Miyasaka, AM Gharehbaghi 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), 744-749, 2020 | 2 | 2020 |
| Automatically adjusting system level designs after RTL/gate-level ECO Q Wang, Y Kimura, M Fujita 2016 IEEE International High Level Design Validation and Test Workshop …, 2016 | 2 | 2016 |
| Parallelizing quantum simulation with decision diagrams S Li, Y Kimura, H Sato, M Fujita IEEE Transactions on Quantum Engineering, 2024 | 1 | 2024 |
| Q&A MAESTRO: Q&A post recommendation for fixing Java runtime exceptions Y Kimura, T Akazaki, S Kikuchi, S Mahajan, MR Prasad 2021 36th IEEE/ACM International Conference on Automated Software …, 2021 | 1 | 2021 |
| Signal selection methods for debugging gate-level sequential circuits Y Kimura, AM Gharehbaghi, M Fujita IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and …, 2019 | 1 | 2019 |
| C Description Reconstruction Method from a Revised Netlist for ECO Support Y Kimura, AM Gharehbaghi, M Fujita IEICE Transactions on Fundamentals of Electronics, Communications and …, 2018 | 1 | 2018 |
| High-Level Debugging of Post-Silicon Failures M Fujita, Q Wang, Y Kimura Post-Silicon Validation and Debug, 231-253, 2019 | | 2019 |
| Specification by existing design plus use-cases Y Kimura, M Fujita 2016 IEEE International High Level Design Validation and Test Workshop …, 2016 | | 2016 |
Masahiro FujitaUniversity of TokyoVerified email at ee.t.u-tokyo.ac.jp
