Follow
Ran Wang
Ran Wang
Verified email at nvidia.com
Title
Cited by
Cited by
Year
Scan-based testing of post-bond silicon interposer interconnects in 2.5-D ICs
R Wang, K Chakrabarty, B Eklow
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2014
282014
A programmable method for low-power scan shift in SoC integrated circuits
R Wang, B Bhaskaran, K Natarajan, A Abdollahian, K Narayanun, ...
2016 IEEE 34th VLSI Test Symposium (VTS), 1-6, 2016
242016
Built-in self-test and test scheduling for interposer-based 2.5 D IC
R Wang, K Chakrabarty, S Bhawmik
ACM Transactions on Design Automation of Electronic Systems (TODAES) 20 (4 …, 2015
232015
Interconnect testing and test-path scheduling for interposer-based 2.5-D ICs
R Wang, K Chakrabarty, S Bhawmik
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2014
222014
Test and design-for-testability solutions for 3D integrated circuits
K Chakrabarty, M Agrawal, S Deutsch, B Noia, R Wang, F Ye
IPSJ Transactions on System and LSI Design Methodology 7, 56-73, 2014
222014
Pre-bond testing of the silicon interposer in 2.5 D ICs
R Wang, Z Li, S Kannan, K Chakrabarty
2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 978-983, 2016
202016
At-speed interconnect testing and test-path optimization for 2.5 D ICs
R Wang, K Chakrabarty, S Bhawmik
2014 IEEE 32nd VLSI Test Symposium (VTS), 1-6, 2014
202014
Built-in self-test, diagnosis, and repair of multimode power switches
R Wang, Z Zhang, X Kavousianos, Y Tsiatouhas, K Chakrabarty
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2014
162014
Post-bond Testing of the Silicon Interposer and Micro-bumps in 2.5 D ICs
R Wang, K Chakrabarty, B Eklow
2013 22nd Asian Test Symposium, 147-152, 2013
162013
Multi-layer integrated circuits having isolation cells for layer testing and related methods
K Chakrabarty, R Wang
US Patent 10,338,133, 2019
112019
Modeling and compare of through-silicon-via (TSV) in high frequency
R Wang, G Charles, P Franzon
2011 IEEE International 3D Systems Integration Conference (3DIC), 2011 IEEE …, 2012
102012
Tackling test challenges for interposer-based 2.5-D integrated circuits
R Wang, K Chakrabarty
IEEE Design & Test 34 (5), 72-79, 2017
92017
Testing of interposer-based 2.5 D integrated circuits
R Wang, K Chakrabarty
2016 IEEE International Test Conference (ITC), 1-10, 2016
92016
Prebond testing and test-path design for the silicon interposer in 2.5-D ICs
R Wang, Z Li, S Kannan, K Chakrabarty
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2016
82016
ExTest scheduling for 2.5 D system-on-chip integrated circuits
R Wang, G Li, R Li, J Qian, K Chakrabarty
2015 IEEE 33rd VLSI Test Symposium (VTS), 1-6, 2015
82015
The hype, myths, and realities of testing 3D integrated circuits
R Wang, S Deutsch, M Agrawal, K Chakrabarty
2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-8, 2016
62016
A design-for-test solution for monolithic 3D integrated circuits
R Wang, K Chakrabarty
2016 21th IEEE European Test Symposium (ETS), 1-6, 2016
52016
Multicast test architecture and test scheduling for interposer-based 2.5 D ICs
S Wang, R Wang, K Chakrabarty, MB Tahoori
2016 IEEE 25th Asian Test Symposium (ATS), 86-91, 2016
42016
ExTest Scheduling and Optimization for 2.5-D SoCs With Wrapped Tiles
R Wang, G Li, R Li, J Qian, K Chakrabarty
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2016
42016
Built-in self-test for interposer-based 2.5 D ICs
R Wang, K Chakrabarty, S Bhawmik
2014 IEEE 32nd International Conference on Computer Design (ICCD), 181-188, 2014
42014
The system can't perform the operation now. Try again later.
Articles 1–20