Brett H Meyer
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Neural networks designing neural networks: multi-objective hyper-parameter optimization
SC Smithson, G Yang, WJ Gross, BH Meyer
2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-8, 2016
Architecture implications of pads as a scarce resource
R Zhang, K Wang, BH Meyer, MR Stan, K Skadron
ACM SIGARCH Computer Architecture News 42 (3), 373-384, 2014
Efficient CMOS invertible logic using stochastic computing
SC Smithson, N Onizawa, BH Meyer, WJ Gross, T Hanyu
IEEE Transactions on Circuits and Systems I: Regular Papers 66 (6), 2263-2274, 2019
ArchFP: Rapid prototyping of pre-RTL floorplans
GG Faust, R Zhang, K Skadron, MR Stan, BH Meyer
2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip …, 2012
A case for lifetime-aware task mapping in embedded chip multiprocessors
AS Hartman, DE Thomas, BH Meyer
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware …, 2010
Power-performance simulation and design strategies for single-chip heterogeneous multiprocessors
BH Meyer, JJ Pieper, JM Paul, JE Nelson, SM Pieper, AG Rowe
IEEE transactions on Computers 54 (6), 684-697, 2005
Amdahl’s law revisited for single chip systems
JAM Paul, BH Meyer
International Journal of Parallel Programming 35, 101-123, 2007
A four-mode model for efficient fault-tolerant mixed-criticality systems
Z Al-bayati, J Caplan, BH Meyer, H Zeng
2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 97-102, 2016
Stochastic computing can improve upon digital spiking neural networks
SC Smithson, K Boga, A Ardakani, BH Meyer, WJ Gross
2016 IEEE International Workshop on Signal Processing Systems (SiPS), 309-314, 2016
Cost-effective slack allocation for lifetime improvement in NoC-based MPSoCs
BH Meyer, AS Hartman, DE Thomas
2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010 …, 2010
Using speech synthesis to train end-to-end spoken language understanding models
L Lugosch, BH Meyer, D Nowrouzezahrai, M Ravanelli
ICASSP 2020-2020 IEEE International Conference on Acoustics, Speech and …, 2020
Learning recurrent binary/ternary weights
A Ardakani, Z Ji, SC Smithson, BH Meyer, WJ Gross
arXiv preprint arXiv:1809.11086, 2018
Some limits of power delivery in the multicore era
R Zhang, BH Meyer, W Huang, K Skadron, MR Stan
Proc. WEED, 1-7, 2012
Cost-effective safety and fault localization using distributed temporal redundancy
BH Meyer, BH Calhoun, J Lach, K Skadron
Proceedings of the 14th international conference on Compilers, architectures …, 2011
Evaluating overheads of multibit soft-error protection in the processor core
LG Szafaryn, BH Meyer, K Skadron
IEEE Micro 33 (4), 56-65, 2013
Temperature-to-power mapping
Z Qi, BH Meyer, W Huang, RJ Ribando, K Skadron, MR Stan
2010 IEEE International Conference on Computer Design, 384-389, 2010
Mapping and scheduling mixed-criticality systems with on-demand redundancy
J Caplan, Z Al-Bayati, H Zeng, BH Meyer
IEEE Transactions on Computers 67 (4), 582-588, 2017
Efficient fine-tuning of BERT models on the edge
D Vucetic, M Tayaranian, M Ziaeefard, JJ Clark, BH Meyer, WJ Gross
2022 IEEE International Symposium on Circuits and Systems (ISCAS), 1838-1842, 2022
In-hardware training chip based on CMOS invertible logic for machine learning
N Onizawa, SC Smithson, BH Meyer, WJ Gross, T Hanyu
IEEE Transactions on Circuits and Systems I: Regular Papers 67 (5), 1541-1550, 2019
Cost-effective lifetime and yield optimization for NoC-based MPSoCs
BH Meyer, AS Hartman, DE Thomas
ACM Transactions on Design Automation of Electronic Systems (TODAES) 19 (2 …, 2014
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