Brett H Meyer

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Kevin SkadronHarry Douglas Forsyth Professor of Computer Science, University of VirginiaVerified email at virginia.edu
Mircea R. StanVirginia Microelectronics Consortium (VMEC) Professor, University of VirginiaVerified email at virginia.edu
Runjie ZhangEDA, OracleVerified email at oracle.com
Ke WangUniversity of VirginiaVerified email at virginia.edu
Haibo ZengElectrical & Computer Engineering, Virginia TechVerified email at vt.edu
Zaid Al-bayatiMcGill UniversityVerified email at mail.mcgill.ca
JoAnn M. PaulAssociate Professor of Electrical and Computer Engineering, Virginia TechVerified email at vt.edu
Wei HuangAMD Research, IBM Research, University of Virginia, University of Science and Technology of ChinaVerified email at amd.com
Dimitrios SoudrisProfessor, Electrical & Computer Eng., National Technical Univ. of AthensVerified email at microlab.ntua.gr
Dimitrios RodopoulosGraphcoreVerified email at graphcore.ai
Zeljko ZilicProfessor of Electrical and Computer EngineeringVerified email at mcgill.ca
Dimitrios StamoulisMicrosoftVerified email at microsoft.com
John LachThe George Washington UniversityVerified email at gwu.edu
Benton CalhounProfessor of Electrical and Computer Engineering, University of VirginiaVerified email at virginia.edu
Qi ZhuAssociate Professor of Electrical Engineering and Computer ScienceVerified email at northwestern.edu
Marco Di NataleFull Professor, TECIP Institute, Scuola Superiore S. AnnaVerified email at sssup.it
Jürgen TeichFull Professor, Computer Science, Friedrich-Alexander-Universität Erlangen-NürnbergVerified email at cs.fau.de
vahid lariUniversity of Erlangen-NurembergVerified email at cs.fau.de
Alexandru TanaseFriedrich-Alexander-Universität Erlangen-NürnbergVerified email at cs.fau.de
Karthik SankaranarayananIntelVerified email at intel.com

Brett H Meyer

McGill University

Verified email at mcgill.ca - Homepage

Computer architecture electronic design automation fault-tolerance embedded system security machine learning


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Architecture implications of pads as a scarce resource R Zhang, K Wang, BH Meyer, MR Stan, K Skadron 2014 ACM/IEEE 41st International Symposium on Computer Architecture (ISCA …, 2014	73	2014
Neural networks designing neural networks: multi-objective hyper-parameter optimization SC Smithson, G Yang, WJ Gross, BH Meyer Proceedings of the 35th International Conference on Computer-Aided Design, 1-8, 2016	52	2016
Power-performance simulation and design strategies for single-chip heterogeneous multiprocessors BH Meyer, JJ Pieper, JAM Paul, JE Nelson, SM Pieper, AG Rowe IEEE transactions on Computers 54 (6), 684-697, 2005	51	2005
A case for lifetime-aware task mapping in embedded chip multiprocessors AS Hartman, DE Thomas, BH Meyer Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware …, 2010	48	2010
Amdahl’s law revisited for single chip systems JAM Paul, BH Meyer International Journal of Parallel Programming 35 (2), 101-123, 2007	48	2007
ArchFP: Rapid prototyping of pre-RTL floorplans GG Faust, R Zhang, K Skadron, MR Stan, BH Meyer 2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip …, 2012	45	2012
Cost-effective slack allocation for lifetime improvement in NoC-based MPSoCs BH Meyer, AS Hartman, DE Thomas 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010 …, 2010	42	2010
A four-mode model for efficient fault-tolerant mixed-criticality systems Z Al-bayati, J Caplan, BH Meyer, H Zeng 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 97-102, 2016	32	2016
Some limits of power delivery in the multicore era R Zhang, BH Meyer, W Huang, K Skadron, MR Stan Proc. WEED, 1-7, 2012	31	2012
Evaluating overheads of multibit soft-error protection in the processor core LG Szafaryn, BH Meyer, K Skadron IEEE Micro 33 (4), 56-65, 2013	27	2013
Stochastic computing can improve upon digital spiking neural networks SC Smithson, K Boga, A Ardakani, BH Meyer, WJ Gross 2016 IEEE International Workshop on Signal Processing Systems (SiPS), 309-314, 2016	25	2016
Temperature-to-power mapping Z Qi, BH Meyer, W Huang, RJ Ribando, K Skadron, MR Stan 2010 IEEE International Conference on Computer Design, 384-389, 2010	25	2010
Cost-effective safety and fault localization using distributed temporal redundancy BH Meyer, BH Calhoun, J Lach, K Skadron Proceedings of the 14th international conference on Compilers, architectures …, 2011	22	2011
Learning recurrent binary/ternary weights A Ardakani, Z Ji, SC Smithson, BH Meyer, WJ Gross arXiv preprint arXiv:1809.11086, 2018	20	2018
Cost-effective lifetime and yield optimization for NoC-based MPSoCs BH Meyer, AS Hartman, DE Thomas ACM Transactions on Design Automation of Electronic Systems (TODAES) 19 (2 …, 2014	20	2014
Simultaneous synthesis of buses, data mapping and memory allocation for MPSoC BH Meyer, DE Thomas Proceedings of the 5th IEEE/ACM international conference on Hardware …, 2007	19	2007
Efficient CMOS invertible logic using stochastic computing SC Smithson, N Onizawa, BH Meyer, WJ Gross, T Hanyu IEEE Transactions on Circuits and Systems I: Regular Papers 66 (6), 2263-2274, 2019	18	2019
Fault-tolerant scheduling of multicore mixed-criticality systems under permanent failures Z Al-bayati, BH Meyer, H Zeng 2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and …, 2016	18	2016
Walking pads: Fast power-supply pad-placement optimization K Wang, BH Meyer, R Zhang, K Skadron, M Stan 2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC), 537-543, 2014	17	2014
Rethinking automated synthesis of MPSoC architectures BH Meyer, DE Thomas 2007 IEEE International Parallel and Distributed Processing Symposium, 1-6, 2007	17	2007

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