| Real-time fault-tolerance with hot-standby topology for conditional sum adder A Mukherjee, AS Dhar Microelectronics Reliability 55 (3-4), 704-712, 2015 | 34 | 2015 |
| A highly robust and low-power real-time double node upset self-healing latch for radiation-prone applications S Kumar, A Mukherjee IEEE Transactions on Very Large Scale Integration (VLSI) Systems 29 (12 …, 2021 | 24 | 2021 |
| Triple transistor based triple modular redundancy with embedded voter circuit A Mukherjee, AS Dhar Microelectronics journal 87, 101-109, 2019 | 11 | 2019 |
| A Self-Healing, High Performance and Low-Cost Radiation Hardened Latch Design S Kumar, A Mukherjee 2021 IEEE International Symposium on Defect and Fault Tolerance in VLSI and …, 2021 | 10 | 2021 |
| Design of a Self-Reconfigurable Adder for Fault-Tolerant VLSI Architecture A Mukherjee, AS Dhar 2012 International Symposium on Electronic System Design (ISED), 92-96, 2012 | 10 | 2012 |
| FPGA-Based Low-Cost Architecture for R-Peak Detection and Heart-Rate Calculation Using Lifting-Based Discrete Wavelet Transform A Gon, A Mukherjee Circuits, Systems, and Signal Processing 42 (1), 580-600, 2023 | 8 | 2023 |
| Triple transistor based fault tolerance for resource constrained applications A Mukherjee, AS Dhar Microelectronics journal 68, 1-6, 2017 | 8 | 2017 |
| New triple-transistor based defect-tolerant systems for reliable digital architectures A Mukherjee, AS Dhar 2015 IEEE International Symposium on Circuits and Systems (ISCAS), 1917-1920, 2015 | 8 | 2015 |
| Fault tolerant architecture design using quad‐gate‐transistor redundancy A Mukherjee, AS Dhar IET Circuits, Devices & Systems 9 (3), 152-160, 2015 | 8 | 2015 |
| Design of a fault-tolerant conditional sum adder A Mukherjee, AS Dhar Progress in VLSI Design and Test: 16th International Symposium, VDAT 2012 …, 2012 | 8 | 2012 |
| A triple-node upset self-healing latch for high speed and robust operation in radiation-prone harsh-environment S Kumar, A Mukherjee Microelectronics Reliability 139, 114857, 2022 | 7 | 2022 |
| Design of low power stacked inverter based sram cell with improved write ability D Chaudhary, V Muppalla, A Mukheerjee 2020 IEEE Region 10 Symposium (TENSYMP), 925-928, 2020 | 7 | 2020 |
| Effect of Fin Width and Fin Height on Threshold Voltage for Tripple Gate Rectangular FinFET S Banerjee, E Sarkar, A Mukherjee Techno International Journal of Health, Engineering. Manage. Sci, 2018 | 7 | 2018 |
| Design of soft-error resilient SRAM cell with high read and write stability for robust operations S Kumar, A Mukherjee AEU-International Journal of Electronics and Communications 168, 154719, 2023 | 6 | 2023 |
| Double-fault tolerant architecture design for digital adder A Mukherjee, AS Dhar Proceedings of the 2014 IEEE Students' Technology Symposium, 154-158, 2014 | 6 | 2014 |
| VLSI Architecture Design of Motion Estimation Block with Hexagon-Diamond Search Pattern for Real-Time Video Processing A Mukherjee IEEE 18th India Council International Conference (INDICON), 1-6, 2021 | 4 | 2021 |
| Choice of granularity for reliable circuit design using dynamic reconfiguration A Mukherjee, AS Dhar Microelectronics Reliability 63, 291-303, 2016 | 4 | 2016 |
| Removal of Noises from an ECG Signal Using an Adaptive S-Median Thresholding Technique A Gon, A Mukherjee 2020 IEEE Applied Signal Processing Conference (ASPCON), 89-93, 2020 | 3 | 2020 |
| A New Power-Gated Hybrid Defect Tolerant Approach Based on Modular Redundancy S Pal, A Mukherjee 2021 Asian Conference on Innovation in Technology (ASIANCON), 1-4, 2021 | 2 | 2021 |
| Defect tolerant approach for reliable majority voter design using quadded transistor logic A Mukherjee 2020 IEEE REGION 10 CONFERENCE (TENCON), 165-169, 2020 | 2 | 2020 |
Anindya Sundar DharProfessor, Dept. of Electronics and Electrical Communication Engineering, Indian Institute ofVerified email at ece.iitkgp.ernet.in
