| P4-compatible high-level synthesis of low latency 100 Gb/s streaming packet parsers in FPGAs J Santiago da Silva, FR Boyer, JMP Langlois Proceedings of the 2018 ACM/SIGDA International Symposium on Field …, 2018 | 49 | 2018 |
| Extern objects in p4: an rohc header compression scheme case study JS da Silva, FR Boyer, LO Chiquette, JMP Langlois 2018 4th IEEE Conference on Network Softwarization and Workshops (NetSoft …, 2018 | 19 | 2018 |
| Module-per-Object: a human-driven methodology for C++-based high-level synthesis design JS da Silva, FR Boyer, JMP Langlois 2019 IEEE 27th Annual International Symposium on Field-Programmable Custom …, 2019 | 13 | 2019 |
| One for all, all for one: A heterogeneous data plane for flexible P4 processing JS da Silva, T Stimpfling, T Luinaud, B Fradj, B Boughzala 2018 IEEE 26th International Conference on Network Protocols (ICNP), 440-441, 2018 | 10 | 2018 |
| Bridging the gap: Fpgas as programmable switches T Luinaud, T Stimpfling, JS da Silva, Y Savaria, JMP Langlois 2020 IEEE 21st International Conference on High Performance Switching and …, 2020 | 9 | 2020 |
| Design principles for packet deparsers on FPGAs T Luinaud, J Santiago da Silva, JMP Langlois, Y Savaria The 2021 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays …, 2021 | 5 | 2021 |
| Area-oriented iterative method for design space exploration with high-level synthesis JS da Silva, S Bampi 2015 IEEE 6th Latin American Symposium on Circuits & Systems (LASCAS), 1-4, 2015 | 5 | 2015 |
| Infraestrutura para controle de projetos em FPGAs através do Protocolo Ethernet JS da Silva, FG Moraes Artigo de Trabalho de Conclusão de Curso, PUCRS, 2011 | 2 | 2011 |
| Unleashing the Power of FPGAs as Programmable Switches T Luinaud, T Stimpfling, J Santiago Da Silva, Y Savaria, JMP Langlois Proceedings of the 2020 ACM/SIGDA International Symposium on Field …, 2020 | | 2020 |
| Fully Programming the Data Plane: A Hardware/Software Approach JS da Silva Ecole Polytechnique, Montreal (Canada), 2020 | | 2020 |
| Architectural exploration of digital systems design for FPGAs using C/C++/SystemC specification languages JS Silva | | 2015 |
J.M. Pierre LangloisPolytechnique Montréal, Génie informatique et génie logicielVerified email at polymtl.ca
