| Semiconductor memory device K Nii, S Obayashi, H Makino, K Ishibashi, H Shinohara US Patent 7,502,275, 2009 | 233 | 2009 |
| An 8.8-ns 54/spl times/54-bit multiplier with high speed redundant binary architecture H Makino, Y Nakase, H Suzuki, H Morinaka, H Shinohara, K Mashiko IEEE Journal of Solid-State Circuits 31 (6), 773-783, 1996 | 230 | 1996 |
| Semiconductor device cell having regularly sized and arranged features H Makino US Patent 6,635,935, 2003 | 209 | 2003 |
| A 65-nm SoC embedded 6T-SRAM designed for manufacturability with read and write operation stabilizing circuits S Ohbayashi, M Yabuuchi, K Nii, Y Tsukamoto, S Imaoka, Y Oda, ... IEEE journal of solid-state circuits 42 (4), 820-829, 2007 | 195 | 2007 |
| A low power SRAM using auto-backgate-controlled MT-CMOS K Nii, H Makino, Y Tujihashi, C Morishima, Y Hayakawa, H Nunogami, ... Proceedings. 1998 International Symposium on Low Power Electronics and …, 1998 | 166 | 1998 |
| Leading-zero anticipatory logic for high-speed floating point addition H Suzuki, H Morinaka, H Makino, Y Nakase, K Mashiko, T Sumi IEEE Journal of Solid-State Circuits 31 (8), 1157-1164, 1996 | 163 | 1996 |
| A 45-nm single-port and dual-port SRAM family with robust read/write stabilizing circuitry under DVFS environment K Nii, M Yabuuchi, Y Tsukamoto, S Ohbayashi, Y Oda, K Usui, ... 2008 IEEE Symposium on VLSI Circuits, 212-213, 2008 | 152 | 2008 |
| A 90-nm low-power 32-kB embedded SRAM with gate leakage suppression circuit for mobile applications K Nii, Y Tsukamoto, T Yoshizawa, S Imaoka, Y Yamagami, T Suzuki, ... IEEE Journal of Solid-State Circuits 39 (4), 684-693, 2004 | 141 | 2004 |
| A 600-MHz 54/spl times/54-bit multiplier with rectangular-styled Wallace tree N Itoh, Y Naemura, H Makino, Y Nakase, T Yoshihara, Y Horiba IEEE Journal of Solid-State Circuits 36 (2), 249-257, 2001 | 92 | 2001 |
| A 65 nm embedded sram with wafer level burn-in mode, leak-bit redundancy and cu e-trim fuse for known good die S Ohbayashi, M Yabuuchi, K Kono, Y Oda, S Imaoka, K Usui, T Yonezu, ... IEEE journal of solid-state circuits 43 (1), 96-108, 2008 | 90 | 2008 |
| A 45-nm bulk CMOS embedded SRAM with improved immunity against process and temperature variations K Nii, M Yabuuchi, Y Tsukamoto, S Ohbayashi, S Imaoka, H Makino, ... IEEE Journal of Solid-State Circuits 43 (1), 180-191, 2008 | 86 | 2008 |
| A 45nm low-standby-power embedded SRAM with improved immunity against process and temperature variations M Yabuuchi, K Nii, Y Tsukamoto, S Ohbayashi, S Imaoka, H Makino, ... 2007 IEEE International Solid-State Circuits Conference. Digest of Technical …, 2007 | 86 | 2007 |
| Synchronous ultra-high-density 2RW dual-port 8T-SRAM with circumvention of simultaneous common-row-access K Nii, Y Tsukamoto, M Yabuuchi, Y Masuda, S Imaoka, K Usui, ... IEEE Journal of Solid-State Circuits 44 (3), 977-986, 2009 | 75 | 2009 |
| A 65 nm SoC embedded 6T-SRAM design for manufacturing with read and write cell stabilizing circuits S Ohbayashi, M Yabuuchi, K Nii, Y Tsukamoto, S Imaoka, Y Oda, ... 2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers., 17-18, 2006 | 71 | 2006 |
| A 90nm dual-port SRAM with 2.04/spl mu/m/sup 2/8T-thin cell using dynamically-controlled column bias scheme K Nii, Y Tsukamoto, T Yoshizawa, S Imaolka, H Makino 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No …, 2004 | 65 | 2004 |
| Semiconductor integrated circuit H Makino, H Suzuki US Patent 6,031,778, 2000 | 65 | 2000 |
| A 8.8-ns 54/spl times/54-bit multiplier using new redundant binary architecture H Makino, Y Nakase, H Shinohara Proceedings of 1993 IEEE International Conference on Computer Design ICCD'93 …, 1993 | 60 | 1993 |
| Worst-case analysis to obtain stable read/write DC margin of high density 6T-SRAM-array with local Vth variability Y Tsukamoto, K Nii, S Imaoka, Y Oda, S Ohbayashi, T Yoshizawa, ... ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005 …, 2005 | 59 | 2005 |
| Reexamination of SRAM cell write margin definitions in view of predicting the distribution H Makino, S Nakata, H Suzuki, S Mutoh, M Miyama, T Yoshimura, ... IEEE Transactions on Circuits and Systems II: Express Briefs 58 (4), 230-234, 2011 | 58 | 2011 |
| An auto-backgate-controlled MT-CMOS circuit H Makino, Y Tsujihashi, K Nii, C Morishima, Y Hayakawa, T Shimizu, ... 1998 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No …, 1998 | 55 | 1998 |
