Daniel Hackenberg
Daniel Hackenberg
Center for Information Services and High Performance Computing (ZIH), TU Dresden
Verified email at tu-dresden.de
Cited by
Cited by
Memory performance and cache coherency effects on an intel nehalem multiprocessor system
D Molka, D Hackenberg, R Schöne, MS Müller
Parallel Architectures and Compilation Techniques, 2009. PACT'09. 18th …, 2009
An energy efficiency feature survey of the intel haswell processor
D Hackenberg, R Schöne, T Ilsche, D Molka, J Schuchart, R Geyer
2015 IEEE international parallel and distributed processing symposium …, 2015
Comparing cache architectures and coherency protocols on x86-64 multicore SMP systems
D Hackenberg, D Molka, WE Nagel
Proceedings of the 42Nd Annual IEEE/ACM International Symposium on …, 2009
Power measurement techniques on standard compute nodes: A quantitative comparison
D Hackenberg, T Ilsche, R Schöne, D Molka, M Schmidt, WE Nagel
2013 IEEE International Symposium on Performance Analysis of Systems and …, 2013
SPEC OMP2012—an application benchmark suite for parallel systems using OpenMP
MS Müller, J Baron, WC Brantley, H Feng, D Hackenberg, R Henschel, ...
International Workshop on OpenMP, 223-236, 2012
HDEEM: high definition energy efficiency monitoring
D Hackenberg, T Ilsche, J Schuchart, R Schöne, WE Nagel, M Simon, ...
Proceedings of the 2nd International Workshop on Energy Efficient …, 2014
Main memory and cache performance of intel sandy bridge and AMD bulldozer
D Molka, D Hackenberg, R Schöne
Proceedings of the workshop on Memory Systems Performance and Correctness, 4, 2014
Characterizing the energy consumption of data transfers and arithmetic operations on x86− 64 processors
D Molka, D Hackenberg, R Schöne, MS Müller
International conference on green computing, 123-133, 2010
Memory Performance at Reduced CPU Clock Speeds: An Analysis of Current x86 64 Processors
R Schöne, D Hackenberg, D Molka
Proceedings of the 2012 USENIX conference on Power-Aware Computing and …, 2012
Cache Coherence Protocol and Memory Performance of the Intel Haswell-EP Architecture
D Molka, D Hackenberg, R Schöne, WE Nagel
Parallel Processing (ICPP), 2015 44th International Conference on, 739-748, 2015
Comprehensive performance tracking with Vampir 7
H Brunst, D Hackenberg, G Juckeland, H Rohling
Tools for High Performance Computing 2009, 17-29, 2010
Introducing FIRESTARTER: A processor stress test utility
D Hackenberg, R Oldenburg, D Molka, R Schöne
2013 International Green Computing Conference Proceedings, 1-9, 2013
The VampirTrace plugin counter interface: introduction and examples
R Schöne, R Tschüter, T Ilsche, D Hackenberg
European Conference on Parallel Processing, 501-511, 2010
Power Measurements for Compute Nodes: Improving Sampling Rates, Granularity and Accuracy
T Ilsche, D Hackenberg, S Graul, R Schöne, J Schuchart
Sixth Int. Green and Sustainable Conputing Conference, 2015
Fast matrix multiplication on Cell (SMP) systems
D Hackenberg
ZIH, TU Dresden, 2007
On-line analysis of hardware performance events for workload characterization and processor frequency scaling decisions
R Schöne, D Hackenberg
Proceedings of the 2nd ACM/SPEC International Conference on Performance …, 2011
Quantifying power consumption variations of HPC systems using SPEC MPI benchmarks
D Hackenberg, R Schöne, D Molka, MS Müller, A Knüpfer
Computer Science-Research and Development 25 (3-4), 155-163, 2010
Detecting Memory-Boundedness with Hardware Performance Counters
D Molka, R Schöne, D Hackenberg, WE Nagel
Proceedings of the 8th ACM/SPEC on International Conference on Performance …, 2017
The READEX formalism for automatic tuning for energy efficiency
J Schuchart, M Gerndt, PG Kjeldsberg, M Lysaght, D Horák, L Říha, ...
Computing, 1-19, 2017
Flexible workload generation for HPC cluster efficiency benchmarking
D Molka, D Hackenberg, R Schöne, T Minartz, WE Nagel
Computer Science-Research and Development 27 (4), 235-243, 2012
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