| Low Power SRAM with Boost Driver Generating Pulsed Word Line Voltage for Sub-1V Operation. M Iijima, K Seto, M Numa, A Tada, T Ipposhi J. Comput. 3 (5), 34-40, 2008 | 38 | 2008 |
| Leakage power reduction for clock gating scheme on PD-SOI K Fukuoka, M Iijima, K Hamada, M Numa, A Tada 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No …, 2004 | 28 | 2004 |
| Boosted voltage scheme with active body-biasing control on pd-soi for ultra low voltage operation M Iijima, M Kitamura, M Numa, A Tada, T Ipposhi, S Maegawa IEICE transactions on electronics 90 (4), 666-674, 2007 | 22 | 2007 |
| Electrochemical analysis of uric acid excretion to the intestinal lumen: effect of serum uric acid-lowering drugs and 5/6 nephrectomy on intestinal uric acid levels K Fujita, H Yamada, M Iijima, K Ichida PloS one 14 (12), e0226918, 2019 | 16 | 2019 |
| Ultra low voltage operation with bootstrap scheme for single power supply SOI-SRAM M Iijima, M Kitamura, M Numa, A Tada, T Ipposhi 20th International Conference on VLSI Design held jointly with 6th …, 2007 | 11 | 2007 |
| Improved write margin for 90nm SOI-7T-SRAM by look-ahead dynamic threshold voltage control M Iijima, K Seto, M Numa, A Tada, T Ipposhi 2007 50th Midwest Symposium on Circuits and Systems, 578-581, 2007 | 7 | 2007 |
| Delayed-ABC SOI for crosstalk noise repair A Tada, H Notani, G Tanaka, T Iwamatsu, T Ipposhi, M Terai, M Iijima, ... IEICE Electronics Express 5 (9), 354-360, 2008 | 3 | 2008 |
| Active body-biasing control technique for bootstrap pass-transistor logic on PD-SOI at 0.5 VV/sub DD M Iijima, M Kitamura, K Hamada, K Fukuoka, M Numa, A Tada, ... 2005 IEEE International SOI Conference Proceedings, 50-51, 2005 | 3 | 2005 |
| A novel layout approach using dual supply voltage technique on body-tied PD-SOI K Fukuoka, M Iijima, K Hamada, M Numa, A Tada IEICE transactions on fundamentals of electronics, communications and …, 2004 | 3 | 2004 |
| Charge recycling in MTCMOS circuits with block dividing A Tada, H Notani, G Tanaka, T Ipposhi, M Iijima, M Numa IEICE Electronics Express 4 (18), 562-568, 2007 | 2 | 2007 |
| High performance CMOS circuit by using charge recycling active body-bias controlled SOI M Kitamura, M Iijima, K Hamada, M Numa, H Notani, A Tada, S Maegawa Integrated Circuit and System Design. Power and Timing Modeling …, 2006 | 2 | 2006 |
| A technique for high-speed circuits on SOI using look-ahead type active body bias control M Iijima, K Fujita, K Fukuoka, M Numa, K Yamamoto, K Takata 2004 IEEE International Symposium on Circuits and Systems (ISCAS) 2, II-405, 2004 | 2 | 2004 |
| A Look-ahead Active Body-biasing scheme for SOI-SRAM with dynamic VDDM control K Seto, M Iijima, T Hirose, M Numa, A Tada, T Ipposhi IEICE Electronics Express 6 (8), 456-460, 2009 | 1 | 2009 |
| Dynamic threshold voltage control for dual supply voltage scheme on PD-SOI M Iijima, K Hamada, M Kitamura, M Numa, A Tada, T Ipposhi IEICE Electronics Express 3 (21), 453-458, 2006 | 1 | 2006 |
| Look-ahead dynamic threshold voltage control scheme for improving write margin of SOI-7T-SRAM M Iijima, K Seto, M Numa, A Tada, T Ipposhi IEICE transactions on fundamentals of electronics, communications and …, 2007 | | 2007 |
| Principles of CMOS VLSI Design Principles of CMOS VLSI Design, 1985 M IIJIMA, M KITAMURA, M NUMA, A TADA, T IPPOSHI, S MAEGAWA IEICE transactions on electronics 90 (4), 666-674, 2007 | | 2007 |
| Bootstrap Pass-Transistor Logic with Active Body-Biasing Control on PD-SOI M Iijima, M Kitamura, K Hamada, M Numa, A Tada, S Maegawa IEICE Technical Report; IEICE Tech. Rep. 105 (476), 31-36, 2005 | | 2005 |
