| RevLib: An online resource for reversible functions and reversible circuits R Wille, D Große, L Teuber, GW Dueck, R Drechsler 38th International Symposium on Multiple Valued Logic (ismvl 2008), 220-225, 2008 | 478 | 2008 |
| Exact multiple-control Toffoli network synthesis with SAT techniques D Große, R Wille, GW Dueck, R Drechsler IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2009 | 211 | 2009 |
| Proving transaction and system-level properties of untimed SystemC TLM designs D Große, HM Le, R Drechsler Eighth ACM/IEEE International Conference on Formal Methods and Models for …, 2010 | 103 | 2010 |
| Equivalence checking of reversible circuits R Wille, D Große, DM Miller, R Drechsler 2009 39th International Symposium on Multiple-Valued Logic, 324-330, 2009 | 96 | 2009 |
| Formal verification of integer multipliers by combining Gröbner basis with logic reduction A Sayed-Ahmed, D Große, U Kühne, M Soeken, R Drechsler 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2016 | 87 | 2016 |
| HW/SW co-verification of embedded systems using bounded model checking D Große, U Kühne, R Drechsler Proceedings of the 16th ACM Great Lakes symposium on VLSI, 43-48, 2006 | 79 | 2006 |
| SWORD: A SAT like prover using word level information R Wille, G Fey, D Große, D Große, S Eggersglüß, R Drechsler VLSI-SoC: Advanced Topics on Systems on a Chip: A Selection of Extended …, 2009 | 67 | 2009 |
| Quantified synthesis of reversible logic R Wille, HM Le, GW Dueck, D Große 2008 Design, Automation and Test in Europe, 1015-1020, 2008 | 65 | 2008 |
| Approximation-aware rewriting of AIGs for error tolerant applications A Chandrasekharan, M Soeken, D Große, R Drechsler 2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-8, 2016 | 64 | 2016 |
| Formal verification of LTL formulas for SystemC designs D Große, R Drechsler Proceedings of the 2003 International Symposium on Circuits and Systems …, 2003 | 64 | 2003 |
| BDD minimization for approximate computing M Soeken, D Große, A Chandrasekharan, R Drechsler 2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC), 474-479, 2016 | 62 | 2016 |
| Verifying SystemC using an intermediate verification language and symbolic simulation HM Le, D Große, V Herdt, R Drechsler Proceedings of the 50th Annual Design Automation Conference, 1-6, 2013 | 62 | 2013 |
| Exact SAT-based Toffoli network synthesis D Große, X Chen, GW Dueck, R Drechsler Proceedings of the 17th ACM Great Lakes symposium on VLSI, 96-101, 2007 | 60 | 2007 |
| Fast exact Toffoli network synthesis of reversible logic R Wille, D Große 2007 IEEE/ACM International Conference on Computer-Aided Design, 60-64, 2007 | 59 | 2007 |
| Quality-Driven SystemC Design D Große, R Drechsler Springer, 2010 | 58 | 2010 |
| Reachability analysis for formal verification of SystemC R Drechsler, D Große Proceedings Euromicro Symposium on Digital System Design. Architectures …, 2002 | 58 | 2002 |
| Extensible and configurable RISC-V based virtual prototype V Herdt, D Große, HM Le, R Drechsler 2018 Forum on Specification & Design Languages (FDL), 5-16, 2018 | 54 | 2018 |
| Exact synthesis of elementary quantum gate circuits for reversible functions with don't cares D Große, R Wille, GW Dueck, R Drechsler 38th International Symposium on Multiple Valued Logic (ismvl 2008), 214-219, 2008 | 54 | 2008 |
| Reversible logic synthesis with output permutation R Wille, D Große, GW Dueck, R Drechsler 2009 22nd International Conference on VLSI Design, 189-194, 2009 | 53 | 2009 |
| CheckSyC: An efficient property checker for RTL SystemC designs D Große, R Drechsler 2005 IEEE International Symposium on Circuits and Systems, 4167-4170, 2005 | 53 | 2005 |
Rolf DrechslerProfessor at University of Bremen, Director DFKI Bremen, GermanyVerified email at uni-bremen.de
