| Tri-gate devices and methods of fabrication RS Chau, BS Doyle, J Kavalieros, D Barlage, S Datta US Patent 7,358,121, 2008 | 564 | 2008 |
| Tri-gate devices and methods of fabrication RS Chau, BS Doyle, J Kavalieros, D Barlage, S Datta, SA Hareland US Patent 6,858,478, 2005 | 500 | 2005 |
| A 50 nm depleted-substrate CMOS transistor (DST) R Chau, J Kavalieros, B Doyle, A Murthy, N Paulsen, D Lionberger, ... International Electron Devices Meeting. Technical Digest (Cat. No. 01CH37224 …, 2001 | 285 | 2001 |
| Transistor Elements for 30nm Physical Gate Lengths and Beyond. B Doyle, R Arghavani, D Barlage, S Datta, M Doczy, J Kavalieros, ... Intel Technology Journal 6 (2), 2002 | 235 | 2002 |
| 30 nm physical gate length CMOS transistors with 1.0 ps n-MOS and 1.7 ps p-MOS gate delays R Chau, J Kavalieros, B Roberds, R Schenker, D Lionberger, D Barlage, ... International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No …, 2000 | 170 | 2000 |
| Tri-gate devices and methods of fabrication RS Chau, BS Doyle, J Kavalieros, D Barlage, S Datta, SA Hareland US Patent 7,005,366, 2006 | 99 | 2006 |
| Methods for nanoscale structures from optical lithography and subsequent lateral growth M Johnson, D Barlage, J Muth US Patent App. 10/550,178, 2007 | 87 | 2007 |
| Plasma nitridation for reduced leakage gate dielectric layers R McFadden, J Kavalieros, R Arghavani, D Barlage, R Chau US Patent 6,610,615, 2003 | 84 | 2003 |
| High-frequency response of 100 nm integrated CMOS transistors with high-K gate dielectrics D Barlage, R Arghavani, G Dewey, M Doczy, B Doyle, J Kavalieros, ... International Electron Devices Meeting. Technical Digest (Cat. No. 01CH37224 …, 2001 | 82 | 2001 |
| IEDM Tech. Dig. R Chau, J Kavalieros, B Roberds, R Schenker, D Lionberger, D Barlage IEDM Tech. Dig, 45, 2000 | 69 | 2000 |
| Zinc oxide thin film transistors with Schottky source barriers AM Ma, M Gupta, FR Chowdhury, M Shen, K Bothe, K Shankar, Y Tsui, ... Solid-State Electronics 76, 104-108, 2012 | 68 | 2012 |
| Tri-gate devices and methods of fabrication RS Chau, BS Doyle, J Kavalieros, D Barlage, S Datta, SA Hareland US Patent 6,914,295, 2005 | 68 | 2005 |
| High-speed InGaP/GaAs HBTs with a strained In/sub x/Ga/sub 1-x/As base DA Ahmari, MT Fresina, QJ Hartmann, DW Barlage, PJ Mares, M Feng, ... IEEE Electron Device Letters 17 (5), 226-228, 1996 | 65 | 1996 |
| Inversion MOS capacitance extraction for high-leakage dielectrics using a transmission line equivalent circuit DW Barlage, JT O'Keeffe, JT Kavalieros, MM Nguyen, RS Chau IEEE Electron Device Letters 21 (9), 454-456, 2000 | 61 | 2000 |
| Method for making a semiconductor device having a high-k gate dielectric RS Chau, TE Glassman, CG Parker, MV Metz, LJ Foley, R Arghavani, ... US Patent 6,713,358, 2004 | 48 | 2004 |
| Effect of Interfacial Roughness Parameters on the Fiber Pushout Behavior of a Model Composite TAPDRBPDJRJ Kerans Journal of the American Ceramic Society 77 (12), 3232-3236, 1994 | 46 | 1994 |
| Electrical Comparison of and Gate Dielectrics on GaN KM Bothe, PA von Hauff, A Afshar, A Foroughi-Abari, KC Cadien, ... IEEE transactions on electron devices 60 (12), 4119-4124, 2013 | 39 | 2013 |
| Schottky Barrier Thin Film Transistors Using Solution-Processed n-ZnO AH Adl, A Ma, M Gupta, M Benlamri, YY Tsui, DW Barlage, K Shankar ACS Applied Materials & Interfaces 4 (3), 1423-1428, 2012 | 38 | 2012 |
| Tri-gate devices and methods of fabrication RS Chau, BS Doyle, J Kavalieros, D Barlage, S Datta US Patent 7,560,756, 2009 | 38 | 2009 |
| Analytical threshold voltage model with TCAD simulation verification for design and evaluation of tri-gate MOSFETs Y Jin, C Zeng, L Ma, D Barlage Solid-state electronics 51 (3), 347-353, 2007 | 35 | 2007 |
Kenneth CadienProfessor of Materials Engineering, University of AlbertaVerified email at ualberta.ca
