| ISPD 2019 initial detailed routing contest and benchmark with advanced routing rules WH Liu, S Mantik, WK Chow, Y Ding, A Farshidi, G Posser Proceedings of the 2019 International Symposium on Physical Design, 147-151, 2019 | 39 | 2019 |
| Buffer sizing for clock networks using robust geometric programming considering variations in buffer sizes L Rakai, A Farshidi, L Behjat, D Westwick Proceedings of the 2013 ACM International symposium on Physical Design, 154-161, 2013 | 17 | 2013 |
| Optimal gate sizing using a self-tuning multi-objective framework A Farshidi, L Rakai, L Behjat, D Westwick Integration 47 (3), 347-355, 2014 | 10 | 2014 |
| Variation-aware geometric programming models for the clock network buffer sizing problem L Rakai, A Farshidi, D Westwick, L Behjat IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2014 | 9 | 2014 |
| A self-tuning multi-objective optimization framework for geometric programming with gate sizing applications A Farshidi, L Rakai, L Behjat, D Westwick Proceedings of the 23rd ACM international conference on Great lakes …, 2013 | 9 | 2013 |
| A pre-placement individual net length estimation model and an application for modern circuits A Farshidi, L Behjat, L Rakai, B Fathi Integration 44 (2), 111-122, 2011 | 7 | 2011 |
| A multiobjective cooptimization of buffer and wire sizes in high-performance clock trees A Farshidi, L Behjat, L Rakai, D Westwick IEEE Transactions on Circuits and Systems II: Express Briefs 64 (4), 412-416, 2016 | 5 | 2016 |
| Variation-aware clock network buffer sizing using robust multi-objective optimization A Farshidi, L Rakai, L Behjat, D Westwick Optimization and Engineering 17, 473-500, 2016 | 4 | 2016 |
| A new a priori net length estimation technique for integrated circuits using radial basis functions A Farshidi, L Rakai, B Samimi, L Behjat, D Westwick Computers & Electrical Engineering 39 (4), 1204-1218, 2013 | 4 | 2013 |
| Power aware resizing of clock tree instances A Farshidi, Z Li US Patent 10,796,066, 2020 | 2 | 2020 |
| Sizing digital circuits using convex optimization techniques L Rakai, A Farshidi Computational intelligence in digital and network designs and applications, 3-32, 2015 | 2 | 2015 |
| A new length-based algebraic multigrid clustering algorithm L Rakai, A Farshidi, L Behjat, D Westwick VLSI Design 2012, 8-8, 2012 | 2 | 2012 |
| Multi-dimension clock gate design in clock tree synthesis A Farshidi, WR Reece, K Han, TA Newton, Z Li US Patent 10,963,618, 2021 | 1 | 2021 |
| Clock cell library selection A Farshidi, Z Li, CJ Alpert, WR Reece US Patent 10,198,551, 2019 | 1 | 2019 |
| Power and Timing Driven Optimal Gate, Clock Buffer and Clock Wire Sizing in High Performance Digital Integrated Circuits A Farshidi | 1 | 2016 |
| Systems and methods for clock tree generation with buffers and inverters A Farshidi, TA Newton, Z Li, CJ Alpert US Patent 10,354,040, 2019 | | 2019 |
| The impact of industry-organized contests on EDA education NK Darav, A Farshidi, AF Tabrizi, E Marasco, A Karbalaei, A Kennings, ... 2015 IEEE International Conference on Microelectronics Systems Education …, 2015 | | 2015 |
| Analysis of post-placement length estimation W Swartz, Y Li, A Farshidi, L Behjat Proceedings of the International Workshop on System Level Interconnect …, 2012 | | 2012 |
| Research Article A New Length-Based Algebraic Multigrid Clustering Algorithm L Rakai, A Farshidi, L Behjat, D Westwick | | 2012 |
| High-Performance Post-Placement Length Estimation Techniques Y LiPPPPPPP, A FarshidiPPPPPPP, L BehjatPPPPPPP, ... | | |
