Amirhossein Mirhosseini
TitleCited byYear
An energy-efficient virtual channel power-gating mechanism for on-chip networks
A Mirhosseini, M Sadrosadati, A Fakhrzadehgan, M Modarressi, ...
2015 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2015
LTRF: Enabling high-capacity register files for GPUs via hardware/software cooperative register prefetching
M Sadrosadati, A Mirhosseini, SB Ehsani, H Sarbazi-Azad, M Drumond, ...
ACM SIGPLAN Notices 53 (2), 489-502, 2018
BiNoCHS: Bimodal network-on-chip for CPU-GPU heterogeneous systems
A Mirhosseini, M Sadrosadati, B Soltani, H Sarbazi-Azad, TF Wenisch
Proceedings of the Eleventh IEEE/ACM International Symposium on Networks-on …, 2017
An efficient dvs scheme for on-chip networks using reconfigurable virtual channel allocators
M Sadrosadati, A Mirhosseini, H Aghilinasab, H Sarbazi-Azad
2015 IEEE/ACM International Symposium on Low Power Electronics and Design …, 2015
Enhancing server efficiency in the face of killer microseconds
A Mirhosseini, A Sriraman, TF Wenisch
2019 IEEE International Symposium on High Performance Computer Architecture …, 2019
Survive: Pointer-based in-DRAM incremental checkpointing for low-cost data persistence and rollback-recovery
A Mirhosseini, A Agrawal, J Torrellas
IEEE Computer Architecture Letters 16 (2), 153-157, 2016
Effective cache bank placement for GPUs
M Sadrosadati, A Mirhosseini, S Roozkhosh, H Bakhishi, H Sarbazi-Azad
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017, 31-36, 2017
The queuing-first approach for tail management of interactive services
A Mirhosseini, TF Wenisch
IEEE Micro 39 (4), 55-64, 2019
Quantifying the difference in resource demand among classic and modern noc workloads
A Mirhosseini, M Sadrosadati, M Zare, H Sarbazi-Azad
2016 IEEE 34th International Conference on Computer Design (ICCD), 404-407, 2016
POSTER: Elastic reconfiguration for heterogeneous NoCs with BiNoCHS
A Mirhosseini, M Sadrosadati, B Soltani, H Sarbazi-Azad, TF Wenisch
2017 26th International Conference on Parallel Architectures and Compilation …, 2017
BARAN: Bimodal adaptive reconfigurable-allocator network-on-chip
A Mirhosseini, M Sadrosadati, F Aghamohammadi, M Modarressi, ...
ACM Transactions on Parallel Computing (TOPC) 5 (3), 1-29, 2019
Express-Lane Scheduling and Multithreading to Minimize the Tail Latency of Microservices
A Mirhosseini, BL West, GW Blake, TF Wenisch
2019 IEEE International Conference on Autonomic Computing (ICAC), 194-199, 2019
Software Data Planes: You Can't Always Spin to Win
H Golestani, A Mirhosseini, TF Wenisch
Proceedings of the ACM Symposium on Cloud Computing, 337-350, 2019
Cooperating multithreaded processor and mode-selectable processor
S Mirhosseininiri, TF Wenisch
US Patent App. 15/888,359, 2019
Hiding the Microsecond-Scale Latency of Storage-Class Memories with Duplexity
AMA Sriraman, TF Wenisch
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