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Rafael Billig Tonetto
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Precise evaluation of the fault sensitivity of OoO superscalar processors
RB Tonetto, GL Nazar, ACS Beck
2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), 613-616, 2018
72018
A knapsack methodology for hardware-based dmr protection against soft errors in superscalar out-of-order processors
RB Tonetto, DM Cardoso, M Brandalero, L Agostini, GL Nazar, ...
2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration …, 2019
42019
Improving software-based techniques for soft error mitigation in OoO superscalar processors
DM Cardoso, RB Tonetto, M Brandalero, L Agostini, GL Nazar, ...
2019 26th IEEE International Conference on Electronics, Circuits and Systems …, 2019
32019
Exploring the limitations of dataflow sihft techniques in out-of-order superscalar processors
DM Cardoso, R Tonetto, M Brandalero, G Nazar, AC Beck, JR Azambuja
Microelectronics Reliability 100, 113406, 2019
32019
Snap: Selective ntv heterogeneous architectures for power-efficient edge computing
RB Tonetto, ACS Beck, GL Nazar
2022 25th Euromicro Conference on Digital System Design (DSD), 357-364, 2022
22022
A reliability-oriented machine learning strategy for heterogeneous multicore application mapping
RB Tonetto, MGA Hiago, B Zatt, ACS Beck, GL Nazar
2020 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2020
12020
A machine learning approach for reliability-aware application mapping for heterogeneous multicores
RB Tonetto, MGA Hiago, GL Nazar, ACS Beck
2020 57th ACM/IEEE Design Automation Conference (DAC), 1-6, 2020
12020
A reliability-and variation-aware methodology for improved processor designs for the edge computing domain
RB Tonetto
2023
A platform to evaluate the fault sensitivity of superscalar processors
RB Tonetto
2017
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Articles 1–9