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Amer Samarah
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A digital phase-locked loop with calibrated coarse and stochastic fine TDC
A Samarah, AC Carusone
IEEE journal of solid-state circuits 48 (8), 1829-1841, 2013
832013
Automated coverage directed test generation using a cell-based genetic algorithm
A Samarah, A Habibi, S Tahar, N Kharma
2006 IEEE International High Level Design Validation and Test Workshop, 19-26, 2006
632006
Efficient assertion based verification using TLM
A Habibi, S Tahar, A Samarah, D Li, OA Mohamed
Proceedings of the Design Automation & Test in Europe Conference 1, 1-6, 2006
272006
Multi-phase bang-bang digital phase lock loop with accelerated frequency acquisition
A Samarah, AC Carusone
2015 IEEE International Symposium on Circuits and Systems (ISCAS), 545-548, 2015
82015
Towards a faster simulation of SystemC designs
A Habibi, H Moinudeen, A Samarah, S Tahar
IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and …, 2006
52006
Cycle-slipping pull-in range of bang-bang PLLs
A Samarah, AC Carusone
2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS), 1-4, 2015
32015
A dead-zone free and linearized digital PLL
A Samarah, AC Carusone
2012 19th IEEE International Conference on Electronics, Circuits, and …, 2012
32012
Improved Phase Detection for Digital Phase-Locked Loops
A Samarah
University of Toronto (Canada), 2016
2016
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Articles 1–8