Hossein Asadi
Hossein Asadi
Professor, Department of Computer Engineering, Sharif University of Technology
Verified email at - Homepage
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Balancing performance and reliability in the memory hierarchy
GH Asadi, V Sridharan, MB Tahoori, D Kaeli
Performance Analysis of Systems and Software, 2005. ISPASS 2005. IEEE …, 2005
Soft error rate estimation and mitigation for SRAM-based FPGAs
G Asadi, MB Tahoori
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field …, 2005
An analytical approach for soft error rate estimation in digital circuits
G Asadi, MB Tahoori
Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on …, 2005
Soft error rate estimation of digital circuits in the presence of multiple event transients (METs)
M Fazeli, SN Ahmadian, SG Miremadi, H Asadi, MB Tahoori
2011 Design, Automation & Test in Europe, 1-6, 2011
An accurate SER estimation method based on propagation probability [soft error rate]
G Asadi, MB Tahoori
Design, Automation and Test in Europe, 306-307, 2005
Soft error susceptibility analysis of SRAM-based FPGAs in high-performance information systems
H Asadi, MB Tahoori, B Mullins, D Kaeli, K Granlund
IEEE Transactions on Nuclear Science 54 (6), 2714-2726, 2007
Soft error mitigation for SRAM-based FPGAs
GH Asadi, MB Tahoori
23rd IEEE VLSI Test Symposium (VTS'05), 207-212, 2005
A layout-based approach for multiple event transient analysis
M Ebrahimi, H Asadi, MB Tahoori
Proceedings of the 50th Annual Design Automation Conference, 1-6, 2013
Reducing data cache susceptibility to soft errors
V Sridharan, H Asadi, MB Tahoori, D Kaeli
Dependable and Secure Computing, IEEE Transactions on 3 (4), 353-364, 2006
Vulnerability analysis of L2 cache elements to single event upsets
H Asadi, V Sridharan, MB Tahoori, D Kaeli
Proceedings of the Design Automation & Test in Europe Conference 1, 1-6, 2006
Analytical techniques for soft error rate modeling and mitigation of FPGA-based designs
H Asadi, MB Tahoori
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 15 (12 …, 2007
Layout-based modeling and mitigation of multiple event transients
M Ebrahimi, H Asadi, R Bishnoi, MB Tahoori
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2015
Soft error derating computation in sequential circuits
H Asadi, MB Tahoori
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided …, 2006
FPGA-based Protection Scheme against Hardware Trojan Horse Insertion Using Dummy Logic
B Khaleghi, A Ahari, H Asadi, S Bayat Sarmadi
IEEE Embedded Systems Letters, 2015
Efficient algorithms to accurately compute derating factors of digital circuits
H Asadi, MB Tahoori, M Fazeli, SG Miremadi
Microelectronics Reliability 52 (6), 1215-1226, 2012
A hybrid fault injection approach based on simulation and emulation co-operation
A Ejlali, SG Miremadi, H Zarandi, G Asadi, SB Sarmadi
IEEE Computer Society, 2003
An operating system level data migration scheme in hybrid DRAM-NVM memory architecture
R Salkhordeh, H Asadi
2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 936-941, 2016
Soft error modeling and protection for sequential elements
H Asadi, MB Tahoori
20th IEEE International Symposium on Defect and Fault Tolerance in VLSI …, 2005
An analytical approach for soft error rate estimation of SRAM-based FPGAs
G Asadi, MB Tahoori
Proceedings of the Military and Aerospace Applications of Programmable Logic …, 2004
Class: Combined logic and architectural soft error sensitivity analysis
M Ebrahimi, L Chen, H Asadi, MB Tahoori
2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC), 601-607, 2013
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