Ali Khakifirooz
Ali Khakifirooz
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Cited by
Integrated circuit with a thin body field effect transistor and capacitor
K Cheng, B Doris, A Khakifirooz, GG Shahidi
US Patent 8,659,066, 2014
A simple semiempirical short-channel MOSFET current–voltage model continuous across all regions of operation and employing only physical parameters
A Khakifirooz, OM Nayfeh, D Antoniadis
IEEE Transactions on Electron Devices 56 (8), 1674-1680, 2009
High-K/metal gate CMOS finFET with improved pFET threshold voltage
VS Basker, K Cheng, BB Doris, JE Faltermeier, A Khakifirooz
US Patent 7,993,999, 2011
Continuous MOSFET performance increase with device scaling: The role of strain and channel material innovations
DA Antoniadis, I Aberg, CN Chleirigh, OM Nayfeh, A Khakifirooz, JL Hoyt
IBM Journal of Research and Development 50 (4.5), 363-376, 2006
Extremely thin SOI (ETSOI) CMOS with record low variability for low power system-on-chip applications
K Cheng, A Khakifirooz, P Kulkarni, S Ponoth, J Kuss, D Shahrjerdi, ...
2009 IEEE international electron devices meeting (IEDM), 1-4, 2009
ETSOI Technology for 20nm and Beyond
A Khakifirooz
SOI Consortium Workshop: Fully Depleted SOI, 2011
MOSFET performance scaling—Part I: Historical trends
A Khakifirooz, DA Antoniadis
IEEE Transactions on Electron Devices 55 (6), 1391-1400, 2008
Thin semiconductor-on-insulator mosfet with co-integrated silicon, silicon germanium and silicon doped with carbon channels
TN Adam, SW Bedell, K Cheng, BB Doris, A Khakifirooz, A Reznicek, ...
US Patent App. 13/280,850, 2013
Extremely thin semiconductor-on-insulator (ETSOI) FET with a back gate and reduced parasitic capacitance
A Khakifirooz, K Cheng, BB Doris
US Patent 8,507,989, 2013
Integrated circuits including FINFET devices with lower contact resistance and reduced parasitic capacitance and methods for fabricating the same
X Cai, R Xie, A Khakifirooz, K Cheng
US Patent 8,921,191, 2014
Transistor performance scaling: The role of virtual source velocity and its mobility dependence
A Khakifirooz, DA Antoniadis
2006 International Electron Devices Meeting, 1-4, 2006
High performance extremely thin SOI (ETSOI) hybrid CMOS with Si channel NFET and strained SiGe channel PFET
K Cheng, A Khakifirooz, N Loubet, S Luning, T Nagumo, M Vinet, Q Liu, ...
2012 International Electron Devices Meeting, 18.1. 1-18.1. 4, 2012
MOSFET performance scaling—Part II: Future directions
A Khakifirooz, DA Antoniadis
IEEE Transactions on Electron Devices 55 (6), 1401-1408, 2008
Gate-all-around nanowire MOSFET and method of formation
K Cheng, BB Doris, P Hashemi, A Khakifirooz, A Reznicek
US Patent 8,969,934, 2015
Strain scaling for CMOS
SW Bedell, A Khakifirooz, DK Sadana
Mrs Bulletin 39 (2), 131-137, 2014
High performance UTBB FDSOI devices featuring 20nm gate length for 14nm node and beyond
Q Liu, M Vinet, J Gimbert, N Loubet, R Wacquez, L Grenouillet, Y Le Tiec, ...
2013 IEEE International Electron Devices Meeting, 9.2. 1-9.2. 4, 2013
Semiconductor devices fabricated by doped material layer as dopant source
K Cheng, BB Doris, BS Haran, A Khakifirooz, GG Shahidi
US Patent 8,394,710, 2013
Integrated circuit having MOSFET with embedded stressor and method to fabricate same
K Cheng, P Hashemi, A Khakifirooz, A Reznicek
US Patent 8,975,697, 2015
Nanowire transistor structures with merged source/drain regions using auxiliary pillars
P Hashemi, A Khakifirooz, A Reznicek
US Patent 9,257,527, 2016
Junction field effect transistor with an epitaxially grown gate structure
TH Ning, K Cheng, A Khakifirooz, P Kulkarni
US Patent 8,435,845, 2013
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