Pramod Kumar Meher
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50 years of CORDIC: Algorithms, architectures, and applications
PK Meher, J Valls, TB Juang, K Sridharan, K Maharatna
IEEE Transactions on Circuits and Systems I: Regular Papers 56 (9), 1893-1907, 2009
5082009
FPGA realization of FIR filters by efficient and flexible systolization using distributed arithmetic
PK Meher, S Chandrasekaran, A Amira
IEEE transactions on signal processing 56 (7), 3009-3017, 2008
2652008
Efficient integer DCT architectures for HEVC
PK Meher, SY Park, BK Mohanty, KS Lim, C Yeo
IEEE Transactions on Circuits and systems for Video Technology 24 (1), 168-178, 2013
1682013
New approach to look-up-table design and memory-based realization of FIR digital filter
PK Meher
IEEE Transactions on Circuits and Systems I: Regular Papers 57 (3), 592-603, 2009
1502009
Efficient FPGA and ASIC realizations of a DA-based reconfigurable FIR digital filter
SY Park, PK Meher
IEEE Transactions on Circuits and Systems II: Express Briefs 61 (7), 511-515, 2014
1042014
Low-power, high-throughput, and low-area adaptive FIR filter based on distributed arithmetic
SY Park, PK Meher
IEEE Transactions on Circuits and Systems II: Express Briefs 60 (6), 346-350, 2013
1002013
A high-performance energy-efficient architecture for FIR adaptive filter based on new distributed arithmetic formulation of block LMS algorithm
BK Mohanty, PK Meher
IEEE transactions on signal processing 61 (4), 921-932, 2012
922012
Efficient CORDIC algorithms and architectures for low area and high throughput implementation
L Vachhani, K Sridharan, PK Meher
IEEE Transactions on Circuits and Systems II: Express Briefs 56 (1), 61-65, 2009
882009
Nonlinear channel equalization for wireless communication systems using Legendre neural networks
JC Patra, PK Meher, G Chakraborty
Signal Processing 89 (11), 2251-2262, 2009
842009
Hardware-efficient systolization of DA-based calculation of finite digital convolution
PK Meher
IEEE Transactions on Circuits and Systems II: Express Briefs 53 (8), 707-711, 2006
832006
Memory efficient modular VLSI architecture for highthroughput and low-latency implementation of multilevel lifting 2-D DWT
BK Mohanty, PK Meher
IEEE Transactions on signal processing 59 (5), 2072-2084, 2011
762011
FPGA implementation of orthogonal matching pursuit for compressive sensing reconstruction
H Rabah, A Amira, BK Mohanty, S Almaadeed, PK Meher
IEEE Transactions on very large scale integration (VLSI) Systems 23 (10 …, 2014
712014
On Efficient Implementation of Accumulation in Finite Field Over < formula formulatype=
PK Meher
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on 17 (4 …, 2009
71*2009
Systolic and Super-Systolic Multipliers for Finite Field Based on Irreducible Trinomials
PK Meher
IEEE Transactions on Circuits and Systems I: Regular Papers 55 (4), 1031-1040, 2008
702008
CORDIC Designs for Fixed Angle of Rotation
PK Meher, SY Park
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 21 (2), 217-228, 2013
672013
Critical-path analysis and low-complexity implementation of the LMS adaptive algorithm
PK Meher, SY Park
IEEE Transactions on Circuits and Systems I: Regular Papers 61 (3), 778-788, 2013
652013
Memory-Efficient High-Speed Convolution-based Generic Structure for Multilevel 2-D DWT
BK Mohanty, PK Meher
IEEE Transactions on Circuits and Systems for Video Technology 23 (2), 353-363, 2013
652013
Development of Laguerre neural-network-based intelligent sensors for wireless sensor networks
JC Patra, PK Meher, G Chakraborty
IEEE Transactions on instrumentation and measurement 60 (3), 725-734, 2010
622010
LUT optimization for memory-based computation
PK Meher
IEEE Transactions on Circuits and Systems II: Express Briefs 57 (4), 285-289, 2010
622010
Systolic and Non-systolic Scalable Modular Designs of Finite Field Multipliers for Reed-Solomon Codec
PK Meher
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 17 (6), 747-757, 2009
592009
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