Runjie Zhang
Runjie Zhang
EDA, Oracle
Verified email at oracle.com - Homepage
Title
Cited by
Cited by
Year
HotSpot 6.0: Validation, Acceleration and Extension
R Zhang, M Stan, K Skadron
University of Virginia, Tech. Rep. CS-2015-04, 2015
792015
Architecture implications of pads as a scarce resource
R Zhang, K Wang, BH Meyer, MR Stan, K Skadron
2014 ACM/IEEE 41st International Symposium on Computer Architecture (ISCA …, 2014
692014
ArchFP: Rapid prototyping of pre-RTL floorplans
GG Faust, R Zhang, K Skadron, MR Stan, BH Meyer
2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip …, 2012
442012
Some limits of power delivery in the multicore era
R Zhang, BH Meyer, W Huang, K Skadron, MR Stan
Proc. WEED, 1-7, 2012
312012
Walking pads: Fast power-supply pad-placement optimization
K Wang, BH Meyer, R Zhang, K Skadron, M Stan
2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC), 537-543, 2014
172014
A cross-layer design exploration of charge-recycled power-delivery in many-layer 3D-IC
R Zhang, K Mazumdar, BH Meyer, K Wang, K Skadron, M Stan
2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC), 1-6, 2015
142015
Transient voltage noise in charge-recycled power delivery networks for many-layer 3D-IC
R Zhang, K Mazumdar, BH Meyer, K Wang, K Skadron, MR Stan
2015 IEEE/ACM International Symposium on Low Power Electronics and Design …, 2015
132015
Walking pads: Managing C4 placement for transient voltage noise minimization
K Wang, BH Meyer, R Zhang, MR Stan, K Skadron
Proceedings of the 51st Annual Design Automation Conference, 1-6, 2014
122014
System for placement optimization of chip design for transient noise control and related methods thereof
K Wang, K Skadron, MR Stan, R Zhang
US Patent 10,417,367, 2019
62019
Pre-RTL voltage and power optimization for low-cost, thermally challenged multicore chips
A Roelke, R Zhang, K Mazumdar, K Wang, K Skadron, MR Stan
2017 IEEE International Conference on Computer Design (ICCD), 597-600, 2017
62017
Tolerating the consequences of multiple em-induced C4 bump failures
R Zhang, BH Meyer, K Wang, MR Stan, K Skadron
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 24 (6 …, 2015
52015
Hotspot 6.0: Validation, acceleration and extension
M Stan, R Zhang, K Skadron
University of Virginia, Department of Computer Science, 2015
42015
Architecture Implications of Pads as a Scarce Resource: Extended Results
R Zhang, K Wang, BH Meyer, MR Stan, K Skadron
University of Virginia, Tech. Rep. CS-2014-01, 2014
32014
MTTF Enhancement Power-C4 Bump Placement Optimization
S Rahimipour, R Zhang, K Wang, K Skadron, FZB Rokhani, MR Stan
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 27 (7 …, 2019
22019
ArchFP: rapid prototyping of pre-RTL floorplans. VLSISoC
GG Faust, R Zhang, K Skadron, MR Stan, BH Meyer
22012
System, method, and computer readable medium for walking pads: fast power-supply pad-placement optimization
K Wang, K Skadron, MR Stan, R Zhang, B Meyer
US Patent 10,482,210, 2019
12019
Pre-RTL On-Chip Power Delivery Modeling and Analysis
R Zhang
University of Virginia, 2015
12015
System for placement optimization of chip design for transient noise control and related methods thereof
K Wang, K Skadron, MR Stan, R Zhang
US Patent App. 16/571,773, 2020
2020
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