| Understanding Energy Efficiency Benefits of Carbon Nanotube Field-Effect Transistors for Digital VLSI G Hills, MG Bardon, G Doornbos, D Yakimets, P Schuddinck, R Baert, ... IEEE Transactions on Nanotechnology 17 (6), 1259-1269, 2018 | 48 | 2018 |
| Extreme scaling enabled by 5 tracks cells: holistic design-device co-optimization for FinFETs and lateral nanowires M Garcia Bardon, Y Sherazi, P Schuddinck, D Jang, D Yakimets, ... IEEE International Electron Devices Meeting-IEDM, 687-690, 2016 | 45* | 2016 |
| Dynamic time-slot allocation for QoS enabled networks on chip T Marescaux, B Bricke, P Debacker, V Nollet, H Corporaal 3rd Workshop on Embedded Systems for Real-Time Multimedia, 2005., 47-52, 2005 | 43 | 2005 |
| Standard cell design in N7: EUV vs. immersion B Chava, D Rio, Y Sherazi, D Trivkovic, W Gillijns, P Debacker, ... Design-Process-Technology Co-optimization for Manufacturability IX 9427, 94270E, 2015 | 38 | 2015 |
| The impact of sequential-3D integration on semiconductor scaling roadmap A Mallik, A Vandooren, L Witters, A Walke, J Franco, Y Sherazi, P Weckx, ... 2017 IEEE International Electron Devices Meeting (IEDM), 32.1. 1-31.1. 4, 2017 | 30 | 2017 |
| Technology/system codesign and benchmarking for lateral and vertical GAA nanowire FETs at 5-nm technology node C Pan, P Raghavan, D Yakimets, P Debacker, F Catthoor, N Collaert, ... IEEE Transactions on Electron Devices 62 (10), 3125-3132, 2015 | 29 | 2015 |
| Design-technology co-optimization for OxRRAM-based synaptic processing unit A Mallik, D Garbin, A Fantini, D Rodopoulos, R Degraeve, J Stuijt, AK Das, ... 2017 Symposium on VLSI Technology, T178-T179, 2017 | 24 | 2017 |
| Low track height standard cell design in iN7 using scaling boosters SMY Sherazi, C Jha, D Rodopoulos, P Debacker, B Chava, L Matti, ... Design-Process-Technology Co-optimization for Manufacturability XI 10148 …, 2017 | 24 | 2017 |
| An area and energy efficient half-row-paralleled layer LDPC decoder for the 802.11 AD standard M Li, F Naessens, P Debacker, P Raghavan, C Desset, M Li, A Dejonghe, ... SiPS 2013 Proceedings, 112-117, 2013 | 24 | 2013 |
| Architectural strategies in standard-cell design for the 7 nm and beyond technology node SMY Sherazi, B Chava, P Debacker, MG Bardon, P Schuddinck, F Firouzi, ... Journal of Micro/Nanolithography, MEMS, and MOEMS 15 (1), 013507, 2016 | 21 | 2016 |
| Physical Design Solutions to Tackle FEOL/BEOL Degradation in Gate-level Monolithic 3D ICs BW Ku, P Debacker, D Milojevic, P Raghavan, D Verkest, A Thean, ... Proceedings of the 2016 International Symposium on Low Power Electronics and …, 2016 | 18 | 2016 |
| An energy efficient 18Gbps LDPC decoding processor for 802.11 ad in 28nm CMOS M Li, JW Weijers, V Derudder, I Vos, M Rykunov, S Dupont, P Debacker, ... 2015 IEEE Asian Solid-State Circuits Conference (A-SSCC), 1-5, 2015 | 17 | 2015 |
| Embedded ranging system in ISM band X Yin, J Bauwelinck, G Torfs, P Demuytere, J Vandewege, H Tubbax, ... Electronics Letters 44 (17), 1043-1045, 2008 | 15 | 2008 |
| Standard-cell design architecture options below 5nm node: The ultimate scaling of FinFET and Nanosheet SMY Sherazi, M Cupak, P Weckx, O Zografos, D Jang, P Debacker, ... Design-Process-Technology Co-optimization for Manufacturability XIII 10962 …, 2019 | 14 | 2019 |
| DTCO exploration for efficient standard cell power rails B Chava, J Ryckaert, L Mattii, SMY Sherazi, P Debacker, A Spessot, ... Design-Process-Technology Co-optimization for Manufacturability XII 10588 …, 2018 | 14 | 2018 |
| Towards 10000TOPS/W DNN Inference with Analog in-Memory Computing–A Circuit Blueprint, Device Options and Requirements S Cosemans, B Verhoef, J Doevenspeck, IA Papistas, F Catthoor, ... 2019 IEEE International Electron Devices Meeting (IEDM), 22.2. 1-22.2. 4, 2019 | 13 | 2019 |
| Vertical M1 routing-aware detailed placement for congestion and wirelength reduction in sub-10nm nodes P Debacker, K Han, AB Kahng, H Lee, P Raghavan, L Wang 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC), 1-6, 2017 | 13 | 2017 |
| Design and pitch scaling for affordable node transition and EUV insertion scenario R Kim, J Ryckaert, P Raghavan, Y Sherazi, P Debacker, D Trivkovic, ... Design-Process-Technology Co-optimization for Manufacturability XI 10148 …, 2017 | 13 | 2017 |
| On-chip interconnect trends, challenges and solutions: how to keep RC and reliability under control Z Tőkei, I Ciofi, P Roussel, P Debacker, P Raghavan, MH Van Der Veen, ... 2016 IEEE Symposium on VLSI Technology, 1-2, 2016 | 13 | 2016 |
| Integrated circuit power distribution network P Debacker, P Raghavan, VC Gerousis US Patent 10,510,774, 2019 | 12 | 2019 |
Syed Muhammad Yasser SheraziR&D Team Leader, IMECVerified email at imec.be
