Simon Moore
Simon Moore
Professor of Computer Engineering, University of Cambridge
Adresse e-mail validée de cl.cam.ac.uk - Page d'accueil
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Low-latency virtual-channel routers for on-chip networks
R Mullins, A West, S Moore
Proceedings. 31st Annual International Symposium on Computer Architecture …, 2004
5732004
Efficient physical embedding of topologically complex information processing networks in brains and computer circuits
DS Bassett, DL Greenfield, A Meyer-Lindenberg, DR Weinberger, ...
PLoS computational biology 6 (4), 2010
3402010
Improving smart card security using self-timed circuits
S Moore, R Anderson, P Cunningham, R Mullins, G Taylor
Proceedings Eighth International Symposium on Asynchronous Circuits and …, 2002
2322002
A communication characterisation of Splash-2 and Parsec
N Barrow-Williams, C Fensch, S Moore
2009 IEEE International Symposium on Workload Characterization (IISWC), 86-97, 2009
1882009
The CHERI capability model: Revisiting RISC in an age of risk
J Woodruff, RNM Watson, D Chisnall, SW Moore, J Anderson, B Davis, ...
2014 ACM/IEEE 41st International Symposium on Computer Architecture (ISCA …, 2014
1862014
Point to point GALS interconnect
S Moore, G Taylor, R Mullins, P Robinson
Proceedings Eighth International Symposium on Asynchronous Circuits and …, 2002
1682002
The design and implementation of a low-latency on-chip network
R Mullins, A West, S Moore
Asia and South Pacific Conference on Design Automation, 2006., 6 pp., 2006
1582006
The frequency injection attack on ring-oscillator-based true random number generators
AT Markettos, SW Moore
International Workshop on Cryptographic Hardware and Embedded Systems, 317-331, 2009
1422009
Cheri: A hybrid capability-system architecture for scalable software compartmentalization
RNM Watson, J Woodruff, PG Neumann, SW Moore, J Anderson, ...
2015 IEEE Symposium on Security and Privacy, 20-37, 2015
1402015
A power and energy exploration of network-on-chip architectures
A Banerjee, R Mullins, S Moore
First International Symposium on Networks-on-Chip (NOCS'07), 163-172, 2007
1362007
Security evaluation of asynchronous circuits
JJA Fournier, S Moore, H Li, R Mullins, G Taylor
International Workshop on Cryptographic Hardware and Embedded Systems, 137-151, 2003
1132003
Balanced self-checking asynchronous logic for smart card applications
S Moore, R Anderson, R Mullins, G Taylor, JJA Fournier
Microprocessors and Microsystems 27 (9), 421-430, 2003
1102003
Self calibrating clocks for globally asynchronous locally synchronous systems
SW Moore, GS Taylor, PA Cunningham, RD Mullins, P Robinson
Proceedings 2000 International Conference on Computer Design, 73-78, 2000
882000
Demystifying data-driven and pausible clocking schemes
R Mullins, S Moore
13th IEEE International Symposium on Asynchronous Circuits and Systems …, 2007
852007
Bluehive-a field-programable custom computing machine for extreme-scale real-time neural network simulation
SW Moore, PJ Fox, SJT Marsh, AT Markettos, A Mujumdar
2012 IEEE 20th International Symposium on Field-Programmable Custom …, 2012
832012
An energy and performance exploration of network-on-chip architectures
A Banerjee, PT Wolkotte, RD Mullins, SW Moore, GJM Smit
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 17 (3), 319-329, 2009
772009
Beyond the PDP-11: Architectural support for a memory-safe C abstract machine
D Chisnall, C Rothwell, RNM Watson, J Woodruff, M Vadera, SW Moore, ...
ACM SIGARCH Computer Architecture News 43 (1), 117-130, 2015
762015
Implications of Rent's rule for NoC design and its fault-tolerance
D Greenfield, A Banerjee, JG Lee, S Moore
First International Symposium on Networks-on-Chip (NOCS'07), 283-294, 2007
692007
Multithreaded processor design
SW Moore
Springer Science & Business Media, 2012
682012
Security evaluation against electromagnetic analysis at design time
H Li, AT Markettos, S Moore
International Workshop on Cryptographic Hardware and Embedded Systems, 280-292, 2005
652005
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