| Prime: A novel processing-in-memory architecture for neural network computation in reram-based main memory P Chi, S Li, C Xu, T Zhang, J Zhao, Y Liu, Y Wang, Y Xie ACM SIGARCH Computer Architecture News 44 (3), 27-39, 2016 | 852 | 2016 |
| Pinatubo: A processing-in-memory architecture for bulk bitwise operations in emerging non-volatile memories S Li, C Xu, Q Zou, J Zhao, Y Lu, Y Xie Proceedings of the 53rd Annual Design Automation Conference, 1-6, 2016 | 245 | 2016 |
| A 3us wake-up time nonvolatile processor based on ferroelectric flip-flops Y Wang, Y Liu, S Li, D Zhang, B Zhao, MF Chiang, Y Yan, B Sai, H Yang 2012 Proceedings of the ESSCIRC (ESSCIRC), 149-152, 2012 | 213 | 2012 |
| Architecture exploration for ambient energy harvesting nonvolatile processors K Ma, Y Zheng, S Li, K Swaminathan, X Li, Y Liu, J Sampson, Y Xie, ... 2015 IEEE 21st International Symposium on High Performance Computer …, 2015 | 201 | 2015 |
| Drisa: A dram-based reconfigurable in-situ accelerator S Li, D Niu, KT Malladi, H Zheng, B Brennan, Y Xie 2017 50th Annual IEEE/ACM International Symposium on Microarchitecture …, 2017 | 140 | 2017 |
| Ambient energy harvesting nonvolatile processors: From circuit to system Y Liu, Z Li, H Li, Y Wang, X Li, K Ma, S Li, MF Chang, S John, Y Xie, J Shu, ... Proceedings of the 52nd Annual Design Automation Conference, 1-6, 2015 | 116 | 2015 |
| A compression-based area-efficient recovery architecture for nonvolatile processors Y Wang, Y Liu, Y Liu, D Zhang, S Li, B Sai, MF Chiang, H Yang 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2012 | 76 | 2012 |
| NEUTRAMS: Neural network transformation and co-design under neuromorphic hardware constraints Y Ji, YH Zhang, SC Li, P Chi, CH Jiang, P Qu, Y Xie, WG Chen 2016 49th Annual IEEE/ACM International Symposium on Microarchitecture …, 2016 | 61 | 2016 |
| Nonvolatile processor architecture exploration for energy-harvesting applications K Ma, X Li, S Li, Y Liu, JJ Sampson, Y Xie, V Narayanan IEEE Micro 35 (5), 32-40, 2015 | 59 | 2015 |
| PaCC: A parallel compare and compress codec for area reduction in nonvolatile processors Y Wang, Y Liu, S Li, X Sheng, D Zhang, MF Chiang, B Sai, XS Hu, H Yang IEEE Transactions on Very Large Scale Integration (VLSI) Systems 22 (7 …, 2013 | 45 | 2013 |
| A 16Mb dual-mode ReRAM macro with sub-14ns computing-in-memory and memory functions enabled by self-write termination scheme WH Chen, WJ Lin, LY Lai, S Li, CH Hsu, HT Lin, HY Lee, JW Su, Y Xie, ... 2017 IEEE International Electron Devices Meeting (IEDM), 28.2. 1-28.2. 4, 2017 | 38 | 2017 |
| Architecture design with STT-RAM: Opportunities and challenges P Chi, S Li, Y Cheng, Y Lu, SH Kang, Y Xie 2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC), 109-114, 2016 | 34 | 2016 |
| Radar: a 3d-reram based dna alignment accelerator architecture W Huangfu, S Li, X Hu, Y Xie Proceedings of the 55th Annual Design Automation Conference, 1-6, 2018 | 31 | 2018 |
| Nonvolatile processor architectures: Efficient, reliable progress with unstable power K Ma, X Li, K Swaminathan, Y Zheng, S Li, Y Liu, Y Xie, JJ Sampson, ... IEEE Micro 36 (3), 72-83, 2016 | 28 | 2016 |
| Leveraging 3D technologies for hardware security: Opportunities and challenges P Gu, S Li, D Stow, R Barnes, L Liu, Y Xie, E Kursun 2016 International Great Lakes Symposium on VLSI (GLSVLSI), 347-352, 2016 | 27 | 2016 |
| Fpsa: A full system stack solution for reconfigurable reram-based nn accelerator architecture Y Ji, Y Zhang, X Xie, S Li, P Wang, X Hu, Y Zhang, Y Xie Proceedings of the Twenty-Fourth International Conference on Architectural …, 2019 | 24 | 2019 |
| Analysis and optimization of the memory hierarchy for graph processing workloads A Basak, S Li, X Hu, SM Oh, X Xie, L Zhao, X Jiang, Y Xie 2019 IEEE International Symposium on High Performance Computer Architecture …, 2019 | 24 | 2019 |
| Scope: A stochastic computing engine for dram-based in-situ accelerator S Li, AO Glova, X Hu, P Gu, D Niu, KT Malladi, H Zheng, B Brennan, Y Xie 2018 51st Annual IEEE/ACM International Symposium on Microarchitecture …, 2018 | 24 | 2018 |
| Memory trojan attack on neural network accelerators Y Zhao, X Hu, S Li, J Ye, L Deng, Y Ji, J Xu, D Wu, Y Xie 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2019 | 22 | 2019 |
| Neural network model extraction attacks in edge devices by hearing architectural hints X Hu, L Liang, L Deng, S Li, X Xie, Y Ji, Y Ding, C Liu, T Sherwood, Y Xie arXiv preprint arXiv:1903.03916, 2019 | 17 | 2019 |
Yuan XieProfessor of University of California at Santa BarbaraVerified email at ece.ucsb.edu
