| A comparative analysis on the impact of bank contention in STT-MRAM and SRAM based LLCs T Evenblij, M Perumkunnil, F Catthoor, S Sakhare, P Debacker, G Kar, ... 2019 IEEE 37th International Conference on Computer Design (ICCD), 255-263, 2019 | 11 | 2019 |
| Workload-aware electromigration analysis in emerging spintronic memory arrays SM Nair, M Mayahinia, MB Tahoori, M Perumkunnil, H Zahedmanesh, ... IEEE Transactions on Device and Materials Reliability 21 (2), 258-266, 2021 | 7 | 2021 |
| Amped: An analytical model for performance in distributed training of transformers D Moolchandani, J Kundu, F Ruelens, P Vrancx, T Evenblij, ... 2023 IEEE International Symposium on Performance Analysis of Systems and …, 2023 | 3 | 2023 |
| Exploring Pareto-Optimal Hybrid Main Memory Configurations Using Different Emerging Memories SA Chamazcoti, M Gupta, H Oh, T Evenblij, F Catthoor, MP Komalan, ... IEEE Transactions on Circuits and Systems I: Regular Papers 70 (2), 733-746, 2022 | 3 | 2022 |
| Time-Dependent Electromigration Modeling for Workload-Aware Design-Space Exploration in STT-MRAM M Mayahinia, M Tahoori, MP Komalan, H Zahedmanesh, K Croes, ... IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2022 | 3 | 2022 |
| Memory hierarchy calibration based on real hardware in-order cores for accurate simulation Q Huppert, T Evenblij, M Perumkunnil, F Catthoor, L Torres, D Novo 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), 707-710, 2021 | 3 | 2021 |
| A Soft SIMD Based Energy Efficient Computing Microarchitecture P Yu, A Levisse, M Gupta, E Timon, G Ansaloni, F Catthoor, D Atienza arXiv preprint arXiv:2212.09358, 2022 | | 2022 |
| High-Performance Radiation-Hardened Spintronic Retention Latch and Flip-Flop for Highly Reliable Processors SM Nair, M Mayahinia, MB Tahoori, M Perumkunnil, H Zahedmanesh, ... Ieee Transactions On Device And Materials Reliability 21 (2), 258-266, 2021 | | 2021 |
| Analytical Performance Modeling for ARM Processors T Evenblij | | 2017 |
| A Comparative Analysis on the Impact of Bank Contention in STT-MRAM and SRAM Based Last Level Caches T EVENBLIJ, M PERUMKUNNIL, T HUYNH-BAO, F CATTHOOR | | |
