| BRein memory: A single-chip binary/ternary reconfigurable in-memory deep neural network accelerator achieving 1.4 TOPS at 0.6 W K Ando, K Ueyoshi, K Orimo, H Yonekawa, S Sato, H Nakahara, ... IEEE Journal of Solid-State Circuits 53 (4), 983-994, 2017 | 171 | 2017 |
| A lightweight YOLOv2: A binarized CNN with a parallel support vector regression for an FPGA H Nakahara, H Yonekawa, T Fujii, S Sato Proceedings of the 2018 ACM/SIGDA International Symposium on field …, 2018 | 157 | 2018 |
| On-chip memory based binarized convolutional deep neural network applying batch normalization free technique on an FPGA H Yonekawa, H Nakahara 2017 IEEE International Parallel and Distributed Processing Symposium …, 2017 | 105 | 2017 |
| BRein memory: A 13-layer 4.2 K neuron/0.8 M synapse binary/ternary reconfigurable in-memory deep neural network accelerator in 65 nm CMOS K Ando, K Ueyoshi, K Orimo, H Yonekawa, S Sato, H Nakahara, M Ikebe, ... 2017 Symposium on VLSI Circuits, C24-C25, 2017 | 94 | 2017 |
| A memory-based realization of a binarized deep convolutional neural network H Nakahara, H Yonekawa, T Sasao, H Iwamoto, M Motomura 2016 International Conference on Field-Programmable Technology (FPT), 277-280, 2016 | 53 | 2016 |
| An object detector based on multiscale sliding window search using a fully pipelined binarized CNN on an FPGA H Nakahara, H Yonekawa, S Sato 2017 international conference on field programmable technology (ICFPT), 168-175, 2017 | 36 | 2017 |
| A ternary weight binary input convolutional neural network: Realization on the embedded processor H Yonekawa, S Sato, H Nakahara 2018 IEEE 48th International Symposium on Multiple-Valued Logic (ISMVL), 174-179, 2018 | 21 | 2018 |
| GUINNESS: A GUI based binarized deep neural network framework for software programmers H Nakahara, H Yonekawa, T Fujii, M Shimoda, S Sato IEICE TRANSACTIONS on Information and Systems 102 (5), 1003-1011, 2019 | 20 | 2019 |
| A batch normalization free binarized convolutional deep neural network on an FPGA H Nakahara, H Yonekawa, H Iwamoto, M Motomura Proceedings of the 2017 ACM/SIGDA International Symposium on Field …, 2017 | 18 | 2017 |
| Neural network circuit device, neural network, neural network processing method, and neural network execution program H Nakahara, H Yonekawa US Patent App. 16/466,031, 2020 | 10 | 2020 |
| A demonstration of the GUINNESS: A GUI based neural NEtwork SyntheSizer for an FPGA H Nakahara, H Yonekawa, T Fujii, M Shimoda, S Sato 2017 27th International Conference on Field Programmable Logic and …, 2017 | 10 | 2017 |
| In-memory area-efficient signal streaming processor design for binary neural networks H Yonekawa, S Sato, H Nakahara, K Ando, K Ueyoshi, K Hirose, K Orimo, ... 2017 IEEE 60th International Midwest Symposium on Circuits and Systems …, 2017 | 9 | 2017 |
| An on-chip memory batch normalization free binarized convolutional deep neural network on an fpga H Yonekawa, H Nakahara IPDPS, 98-105, 2017 | 8 | 2017 |
| Accelerated Ternarized Deep Neural Network by sparse matrix calculation H Yonekawa, S Sato, H Nakahara, M Motomura IEICE Technical Report; IEICE Tech. Rep. 117 (46), 7-11, 2017 | 2 | 2017 |
| GUINNESS: A GUI based Binarized Deep Neural Network Framework for an FPGA H Nakahara, H Yonekawa, T Fujii, M Shimoda, S Sato IEICE Technical Report; IEICE Tech. Rep. 117 (221), 51-56, 2017 | 1 | 2017 |
| Implementation of Binarized Deep Neural Network for FPGA Considering Power Performance Enhancement H Yonekawa, H Nakahara, M Motomura IEICE Technical Report; IEICE Tech. Rep. 116 (417), 127-132, 2017 | 1 | 2017 |
| Consideration of All Binarized Convolutional Neural Network M Shimoda, T Fujii, H Yonekawa, S Sato, H Nakahara IEICE Technical Report; IEICE Tech. Rep. 117 (153), 131-136, 2017 | | 2017 |
| BRein Memory: バイナリ・インメモリ再構成型深層ニューラルネットワークアクセラレータ K ANDO, A UEYOSHI, K ORIMO, H YONEKAWA, S SATO, H NAKAHARA, ... 電子情報通信学会技術研究報告 117 (166 (SDM2017 31-49)), 101-106, 2017 | | 2017 |
