Andrew Waterman
Andrew Waterman
Verified email at eecs.berkeley.edu
Title
Cited by
Cited by
Year
Roofline: an insightful visual performance model for multicore architectures
S Williams, A Waterman, D Patterson
Communications of the ACM 52 (4), 65-76, 2009
20942009
Single-chip microprocessor that communicates directly using light
C Sun, MT Wade, Y Lee, JS Orcutt, L Alloatti, MS Georgas, AS Waterman, ...
Nature 528 (7583), 534-538, 2015
8802015
Chisel: constructing hardware in a scala embedded language
J Bachrach, H Vo, B Richards, Y Lee, A Waterman, R Avižienis, ...
DAC Design Automation Conference 2012, 1212-1221, 2012
6342012
The rocket chip generator
K Asanovic, R Avizienis, J Bachrach, S Beamer, D Biancolin, C Celio, ...
EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2016-17, 2016
3272016
The risc-v instruction set manual. volume 1: User-level isa, version 2.0
A Waterman, Y Lee, DA Patterson, K Asanovi
California Univ Berkeley Dept of Electrical Engineering and Computer Sciences, 2014
2192014
The RISC-V instruction set manual, volume I: User-level ISA
A Waterman, Y Lee, DA Patterson, K Asanovic
CS Division, EECE Department, University of California, Berkeley, 2014
1942014
RAMP gold: an FPGA-based architecture simulator for multiprocessors
Z Tan, A Waterman, R Avizienis, Y Lee, H Cook, D Patterson, K Asanović
Proceedings of the 47th Design Automation Conference, 463-468, 2010
1532010
The risc-v instruction set manual, volume i: Base user-level isa
A Waterman, Y Lee, DA Patterson, K Asanovic
EECS Department, UC Berkeley, Tech. Rep. UCB/EECS-2011-62 116, 2011
1282011
A 45nm 1.3 GHz 16.7 double-precision GFLOPS/W RISC-V processor with vector accelerators
Y Lee, A Waterman, R Avizienis, H Cook, C Sun, V Stojanović, K Asanović
ESSCIRC 2014-40th European Solid State Circuits Conference (ESSCIRC), 199-202, 2014
1272014
Design of the RISC-V instruction set architecture
AS Waterman
University of California, Berkeley, 2016
1062016
A case for FAME: FPGA architecture model execution
Z Tan, A Waterman, H Cook, S Bird, K Asanović, D Patterson
Proceedings of the 37th annual international symposium on Computer …, 2010
952010
An agile approach to building RISC-V microprocessors
Y Lee, A Waterman, H Cook, B Zimmer, B Keller, A Puggelli, J Kwak, ...
IEEE Micro 36 (2), 8-20, 2016
782016
The risc-v instruction set manual volume 2: Privileged architecture version 1.7
A Waterman, Y Lee, R Avizienis, DA Patterson, K Asanovic
University of California at Berkeley Berkeley United States, 2015
622015
The RISC-V instruction set manual, volume II: Privileged architecture
A Waterman, K Asanovic
RISC-V Foundation. Version 1, 2017
572017
A RISC-V vector processor with simultaneous-switching switched-capacitor DC–DC converters in 28 nm FDSOI
B Zimmer, Y Lee, A Puggelli, J Kwak, R Jevtić, B Keller, S Bailey, ...
IEEE Journal of Solid-State Circuits 51 (4), 930-942, 2016
572016
The rocket chip generator. EECS Department
K Asanovic, R Avizienis, J Bachrach, S Beamer, D Biancolin, C Celio, ...
University of California, Berkeley, Tech. Rep. UCB/EECS-2016-17, 2016
502016
Processes and resource management in a scalable many-core OS
K Klues, B Rhoden, Y Zhu, A Waterman, E Brewer
HotPar10, Berkeley, CA, 106-109, 2010
472010
The RISC-V Reader: an open architecture Atlas
D Patterson, A Waterman
Strawberry Canyon, 2017
452017
A RISC-V vector processor with tightly-integrated switched-capacitor DC-DC converters in 28nm FDSOI
B Zimmer, Y Lee, A Puggelli, J Kwak, R Jevtic, B Keller, S Bailey, ...
2015 Symposium on VLSI Circuits (VLSI Circuits), C316-C317, 2015
392015
Raven: A 28nm RISC-V vector processor with integrated switched-capacitor DC-DC converters and adaptive clocking
Y Lee, B Zimmer, A Waterman, A Puggelli, J Kwak, R Jevtic, B Keller, ...
2015 IEEE Hot Chips 27 Symposium (HCS), 1-45, 2015
192015
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Articles 1–20