Anthony Chan Carusone
Anthony Chan Carusone
Professor of Electrical Engineering, University of Toronto
Verified email at isl.utoronto.ca - Homepage
Title
Cited by
Cited by
Year
Power reduction techniques for LDPC decoders
A Darabiha, A Chan Carusone, FR Kschischang
Solid-State Circuits, IEEE Journal of 43 (8), 1835-1845, 2008
1782008
A bit-serial approximate min-sum LDPC decoder and FPGA implementation
A Darabiha, AC Carusone, FR Kschischang
2006 IEEE International Symposium on Circuits and Systems, 4 pp., 2006
1062006
Multi-Gbit/sec low density parity check decoders with reduced interconnect complexity
A Darabiha, AC Carusone, FR Kschischang
2005 IEEE International Symposium on Circuits and Systems, 5194-5197, 2005
982005
CMOS oscillators for clock distribution and injection-locked deskew
M Hossain, AC Carusone
IEEE Journal of Solid-State Circuits 44 (8), 2138-2153, 2009
952009
Analogue adaptive filters: past and present
A Carusone, DA Johns
IEE Proceedings-Circuits, Devices and Systems 147 (1), 82-90, 2000
912000
Block-interlaced LDPC decoders with reduced interconnect complexity
A Darabiha, AC Carusone, FR Kschischang
IEEE Transactions on Circuits and Systems II: Express Briefs 55 (1), 74-78, 2008
902008
A 30-GS/sec track and hold amplifier in 0.13-μm CMOS technology
S Shahramian, SP Voinigescu, AC Carusone
IEEE Custom Integrated Circuits Conference 2006, 493-496, 2006
802006
A 35-GS/s, 4-bit flash ADC with active data and clock distribution trees
S Shahramian, SP Voinigescu, AC Carusone
IEEE journal of solid-state circuits 44 (6), 1709-1720, 2009
792009
A Digital Phase-Locked Loop with Calibrated Coarse and Stochastic Fine TDC
A Samarah, AC Carusone
Custom Integrated Circuits Conference, 2012
672012
A 3.3-Gbps bit-serial block-interlaced min-sum LDPC decoder in 0.13-μm CMOS
A Darabiha, AC Carusone, FR Kschischang
2007 IEEE Custom Integrated Circuits Conference, 459-462, 2007
642007
A 1-Tap 40-Gb/s Look-Ahead Decision Feedback Equalizer in 0.18-SiGe BiCMOS Technology
A Garg, AC Carusone, SP Voinigescu
Solid-State Circuits, IEEE Journal of 41 (10), 2224-2232, 2006
582006
A 1-tap 40-Gbps look-ahead decision feedback equalizer in 0.18 μm SiGe BiCMOS technology
A Garg, AC Carusone, SP Voinigescu
Compound Semiconductor Integrated Circuit Symposium, 2005. CSIC'05. IEEE, 4 pp., 2005
58*2005
Design Methodology for a 40-GSamples/s Track and Hold Amplifier in 0.18-SiGe BiCMOS Technology
S Shahramian, AC Carusone, SP Voinigescu
Solid-State Circuits, IEEE Journal of 41 (10), 2233-2240, 2006
552006
A 5-Gbit/s CMOS optical receiver with integrated spatially modulated light detector and equalization
TSC Kao, FA Musa, AC Carusone
IEEE Transactions on Circuits and Systems I: Regular Papers 57 (11), 2844-2857, 2010
542010
Design of a dual W-and D-band PLL
S Shahramian, A Hart, A Tomkins, AC Carusone, P Garcia, P Chevalier, ...
IEEE Journal of Solid-State Circuits 46 (5), 1011-1022, 2011
462011
7.4 Gb/s 6.8 mW Source Synchronous Receiver in 65 nm CMOS
M Hossain, A Chan Carusone
Solid-State Circuits, IEEE Journal of 46 (6), 1337-1348, 2011
452011
Differential signaling with a reduced number of signal paths
A Carusone, K Farzan, DA Johns
IEEE Transactions on Circuits and Systems II: Analog and Digital Signal …, 2001
452001
A 3-tap FIR filter with cascaded distributed tap amplifiers for equalization up to 40 Gb/s in 0.18-m CMOS
J Sewter, AC Carusone
Solid-State Circuits, IEEE Journal of 41 (8), 1919-1929, 2006
442006
A 1-1-1-1 MASH delta-sigma modulator with dynamic comparator-based OTAs
K Yamamoto, A Carusone
IEEE Journal of Solid-State Circuits 47 (8), 1866-1883, 2012
432012
Modeling Oscillator Injection Locking Using the Phase Domain Response
D Dunwell, AC Carusone
IEEE Transactions on Circuits and Systems I, 2823-2833, 2013
422013
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Articles 1–20