| NDC: Analyzing the impact of 3D-stacked memory+ logic devices on MapReduce workloads SH Pugsley, J Jestes, H Zhang, R Balasubramonian, V Srinivasan, ... 2014 IEEE International Symposium on Performance Analysis of Systems and …, 2014 | 223 | 2014 |
| Usimm: the utah simulated memory module N Chatterjee, R Balasubramonian, M Shevgoor, S Pugsley, A Udipi, ... University of Utah, Tech. Rep, 1-24, 2012 | 165 | 2012 |
| Efficiently prefetching complex address patterns M Shevgoor, S Koladiya, R Balasubramonian, C Wilkerson, SH Pugsley, ... 2015 48th Annual IEEE/ACM International Symposium on Microarchitecture …, 2015 | 90 | 2015 |
| Sandbox prefetching: Safe run-time evaluation of aggressive prefetchers SH Pugsley, Z Chishti, C Wilkerson, P Chuang, RL Scott, A Jaleel, SL Lu, ... 2014 IEEE 20th International Symposium on High Performance Computer …, 2014 | 82 | 2014 |
| SWEL: Hardware cache coherence protocols to map shared data onto shared caches SH Pugsley, JB Spjut, DW Nellans, R Balasubramonian Proceedings of the 19th international conference on Parallel architectures …, 2010 | 81 | 2010 |
| Comparing implementations of near-data computing with in-memory mapreduce workloads SH Pugsley, J Jestes, R Balasubramonian, V Srinivasan, ... IEEE Micro 34 (4), 44-52, 2014 | 65 | 2014 |
| Path confidence based lookahead prefetching J Kim, SH Pugsley, PV Gratz, ALN Reddy, C Wilkerson, Z Chishti 2016 49th Annual IEEE/ACM International Symposium on Microarchitecture …, 2016 | 58 | 2016 |
| Scalable and reliable communication for hardware transactional memory SH Pugsley, M Awasthi, N Madan, N Muralimanohar, R Balasubramonian 2008 International Conference on Parallel Architectures and Compilation …, 2008 | 53 | 2008 |
| Kill the program counter: Reconstructing program behavior in the processor cache hierarchy J Kim, E Teran, PV Gratz, DA Jiménez, SH Pugsley, C Wilkerson ACM SIGPLAN Notices 52 (4), 737-749, 2017 | 30 | 2017 |
| Perceptron-based prefetch filtering E Bhatia, G Chacon, S Pugsley, E Teran, PV Gratz, DA Jiménez 2019 ACM/IEEE 46th Annual International Symposium on Computer Architecture …, 2019 | 19 | 2019 |
| Memory bandwidth reservation in the cloud to avoid information leakage in the memory controller A Gundu, G Sreekumar, A Shafiee, S Pugsley, H Jain, ... Proceedings of the Third Workshop on Hardware and Architectural Support for …, 2014 | 19 | 2014 |
| Usimm: the utah simulated memory module a simulation infrastructure for the jwac memory scheduling championship N Chatterjee, R Balasubramonian, M Shevgoor, SH Pugsley, AN Udipi, ... | 19 | 2012 |
| Optimizing a multi-core processor for message-passing workloads N Chatterjee, SH Pugsley, J Spjut, R Balasubramonian Proceedings of the Workshop on Unique Chips and Systems (UCAS-5), 2009 | 11 | 2009 |
| Instruction and logic for run-time evaluation of multiple prefetchers ZA Chishti, CB Wilkerson, S Pugsley, P Chuang, RL Scott, A Jaleel, SL Lu, ... US Patent 9,378,021, 2016 | 8 | 2016 |
| Fixed-function hardware sorting accelerators for near data mapreduce execution SH Pugsley, A Deb, R Balasubramonian, F Li 2015 33rd IEEE International Conference on Computer Design (ICCD), 439-442, 2015 | 8 | 2015 |
| Opportunities for near data computing in MapReduce workloads SH Pugsley The University of Utah, 2015 | 4 | 2015 |
| Programmable memory prefetcher for prefetching multiple cache lines based on data in a prefetch engine control register G Venkatesh, CB Wilkerson, SH Pugsley, DT Marr US Patent 10,452,551, 2019 | 3 | 2019 |
| Method and apparatus for pre-fetching data in a system having a multi-level system memory Z Wang, CB Wilkerson, ZA Chishti, SH Pugsley, AR Alameldeen, SLL Lu US Patent 10,108,549, 2018 | 3 | 2018 |
| Multiple subarray memory access N Muralimanohar, NP Jouppi, R Balasubramonian, S Pugsley, ... US Patent App. 13/715,163, 2014 | 3 | 2014 |
| Processor prefetch throttling based on short streams C Zhang, SH Pugsley, MJ Dechene US Patent 10,379,864, 2019 | 2 | 2019 |
Rajeev BalasubramonianProfessor, School of Computing, University of UtahVerified email at cs.utah.edu
