| Stable SRAM cell design for the 32 nm node and beyond L Chang, DM Fried, J Hergenrother, JW Sleight, RH Dennard, ... Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005., 128-129, 2005 | 857 | 2005 |
| High performance and highly uniform gate-all-around silicon nanowire MOSFETs with wire size dependent scaling S Bangsaruntip, GM Cohen, A Majumdar, Y Zhang, SU Engelmann, ... 2009 IEEE International Electron Devices Meeting (IEDM), 1-4, 2009 | 594 | 2009 |
| Hybrid CMOS technology with nanowire devices and double gated planar devices S Bangsaruntip, JB Chang, L Chang, JW Sleight US Patent 8,541,774, 2013 | 394 | 2013 |
| Study of hypernuclei by associated production PH Pile, S Bart, RE Chrien, DJ Millener, RJ Sutter, N Tsoupas, JC Peng, ... Physical review letters 66 (20), 2585, 1991 | 344 | 1991 |
| Gate-all-around silicon nanowire 25-stage CMOS ring oscillators with diameter down to 3 nm S Bangsaruntip, A Majumdar, GM Cohen, SU Engelmann, Y Zhang, ... 2010 symposium on VLSI technology, 21-22, 2010 | 299 | 2010 |
| Microfabrication of a mechanically controllable break junction in silicon C Zhou, CJ Muller, MR Deshpande, JW Sleight, MA Reed Applied Physics Letters 67 (8), 1160-1162, 1995 | 203 | 1995 |
| High-performance CMOS devices on hybrid crystal oriented substrates BB Doris, KW Guarini, M Ieong, S Narasimha, K Rim, JW Sleight, M Yang US Patent 7,329,923, 2008 | 195 | 2008 |
| Universality of short-channel effects in undoped-body silicon nanowire MOSFETs S Bangsaruntip, GM Cohen, A Majumdar, JW Sleight IEEE Electron Device Letters 31 (9), 903-905, 2010 | 184 | 2010 |
| Nanowire mesh device and method of fabricating same SW Bedell, JB Chang, P Chang, MA Guillorn, JW Sleight US Patent 7,893,492, 2011 | 174 | 2011 |
| Single gate inverter nanowire mesh J Chang, P Chang, MA Guillorn, J Sleight US Patent 8,084,308, 2011 | 165 | 2011 |
| Measurement of carrier mobility in silicon nanowires O Gunawan, L Sekaric, A Majumdar, M Rooks, J Appenzeller, JW Sleight, ... Nano letters 8 (6), 1566-1571, 2008 | 164 | 2008 |
| Hybrid crystal orientation CMOS structure for adaptive well biasing and for power and performance enhancement K Bernstein, JW Sleight, M Yang US Patent 7,605,429, 2009 | 146 | 2009 |
| Maskless process for suspending and thinning nanowires S Bangsaruntip, G Cohen, JW Sleight US Patent 7,884,004, 2011 | 139 | 2011 |
| Nanomesh complementary metal-oxide-semiconductor field effect transistors JB Chang, P Chang, MA Guillorn, JW Sleight US Patent App. 13/692,188, 2014 | 128 | 2014 |
| High-performance high-κ/metal gates for 45nm CMOS and beyond with gate-first processing M Chudzik, B Doris, R Mo, J Sleight, E Cartier, C Dewan, D Park, H Bu, ... 2007 IEEE symposium on VLSI technology, 194-195, 2007 | 119 | 2007 |
| Density scaling with gate-all-around silicon nanowire MOSFETs for the 10 nm node and beyond S Bangsaruntip, K Balakrishnan, SL Cheng, J Chang, M Brink, I Lauer, ... 2013 IEEE international electron devices meeting, 20.2. 1-20.2. 4, 2013 | 118 | 2013 |
| Nanowire mesh device and method of fabricating same SW Bedell, JB Chang, P Chang, MA Guillorn, JW Sleight US Patent 7,892,945, 2011 | 114 | 2011 |
| Investigating surface loss effects in superconducting transmon qubits JM Gambetta, CE Murray, YKK Fung, DT McClure, O Dial, W Shanks, ... IEEE Transactions on Applied Superconductivity 27 (1), 1-5, 2016 | 110 | 2016 |
| Role of oxygen vacancies in V/sub FB//V/sub t/stability of pFET metals on HfO/sub 2 E Cartier, FR McFeely, V Narayanan, P Jamison, BP Linder, M Copel, ... Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005., 230-231, 2005 | 109 | 2005 |
| Nanowire mesh FET with multiple threshold voltages J Chang, P Chang, MA Guillorn, J Sleight US Patent 8,422,273, 2013 | 108 | 2013 |
Josephine ChangNorthrop GrummanVerified email at ngc.com
