| A 112 Gb/s PAM-4 56 Gb/s NRZ reconfigurable transmitter with three-tap FFE in 10-nm FinFET J Kim, A Balankutty, RK Dokania, A Elshazly, HS Kim, S Kundu, D Shi, ... IEEE Journal of Solid-State Circuits 54 (1), 29-42, 2018 | 73 | 2018 |
| A 112Gb/s PAM-4 transmitter with 3-Tap FFE in 10nm CMOS J Kim, A Balankutty, R Dokania, A Elshazly, HS Kim, S Kundu, S Weaver, ... 2018 IEEE International Solid-State Circuits Conference-(ISSCC), 102-104, 2018 | 71 | 2018 |
| 8.1 A 224Gb/s DAC-based PAM-4 transmitter with 8-tap FFE in 10nm CMOS J Kim, S Kundu, A Balankutty, M Beach, BC Kim, S Kim, Y Liu, SK Murthy, ... 2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 126-128, 2021 | 61 | 2021 |
| 13.6 A 2.4 GHz WLAN digital polar transmitter with synthesized digital-to-time converter in 14nm trigate/FinFET technology for IoT and wearable applications P Madoglio, H Xu, K Chandrashekar, L Cuellar, M Faisal, WY Li, HS Kim, ... 2017 IEEE International Solid-State Circuits Conference (ISSCC), 226-227, 2017 | 59 | 2017 |
| Adaptive Blocker Rejection Continuous-Time ADC for Mobile WiMAX Applications H Kim, J Lee, T Copani, S Bazarjani, S Kiaei, B Bakkaloglu IEEE Journal of Solid-State Circuits 44 (10), 2766-2779, 2009 | 59 | 2009 |
| A 224-Gb/s DAC-based PAM-4 quarter-rate transmitter with 8-tap FFE in 10-nm FinFET J Kim, S Kundu, A Balankutty, M Beach, BC Kim, ST Kim, Y Liu, SK Murthy, ... IEEE Journal of Solid-State Circuits 57 (1), 6-20, 2021 | 49 | 2021 |
| Sub-picosecond resolution segmented re-circulating stochastic time-to-digital converter A Ravi, O Degani, HS Kim, H Lakdawala, YW Li, P Madoglio US Patent 8,390,349, 2013 | 37 | 2013 |
| A reconfigurable distributed all-digital clock generator core with SSC and skew correction in 22nm high-k tri-gate LP CMOS YW Li, C Ornelas, HS Kim, H Lakdawala, A Ravi, K Soumyanath 2012 IEEE International Solid-State Circuits Conference, 70-72, 2012 | 33 | 2012 |
| A 32 nm SoC with dual core ATOM processor and RF WiFi transceiver H Lakdawala, M Schaecher, CT Fu, R Limaye, J Duster, Y Tan, ... IEEE Journal of Solid-State Circuits 48 (1), 91-103, 2012 | 32 | 2012 |
| Re-circulating time-to-digital converter (TDC) HS Kim, A Ravi, WY Li, K Chandrashekar US Patent 9,197,402, 2015 | 24 | 2015 |
| A 2.4 GHz WLAN transceiver with fully-integrated highly-linear 1.8 V 28.4 dBm PA, 34dBm T/R switch, 240MS/s DAC, 320MS/s ADC, and DPLL in 32nm SoC CMOS Y Tan, J Duster, CT Fu, E Alpman, A Balankutty, C Lee, A Ravi, ... 2012 Symposium on VLSI Circuits (VLSIC), 76-77, 2012 | 24 | 2012 |
| 32nm x86 OS-compliant PC on-chip with dual-core Atom® processor and RF WiFi transceiver H Lakdawala, M Schaecher, C Fu, R Limaye, J Duster, Y Tan, ... 2012 IEEE International Solid-State Circuits Conference, 62-64, 2012 | 23 | 2012 |
| A digital fractional-N PLL with a PVT and mismatch insensitive TDC utilizing equivalent time sampling technique HS Kim, C Ornelas, K Chandrashekar, D Shi, P Su, P Madoglio, WY Li, ... IEEE journal of solid-state circuits 48 (7), 1721-1729, 2013 | 22 | 2013 |
| 11.5 A 23.9-to-29.4 GHz Digital LC-PLL with a Coupled Frequency Doubler for Wireline Applications in 10nm FinFET D Shin, HS Kim, C Liu, P Wali, SK Murthy, Y Fan 2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 188-190, 2021 | 13 | 2021 |
| A 0.13-µm CMOS local oscillator for 60-GHz applications based on push-push characteristic of capacitive degeneration T Copani, H Kim, B Bakkaloglu, S Kiaei 2010 IEEE Radio Frequency Integrated Circuits Symposium, 153-156, 2010 | 12 | 2010 |
| A fractional-N digital LC-PLL using coupled frequency doubler with frequency-tracking loop for wireline applications D Shin, HS Kim, CC Liu, P Wali, SK Murthy, Y Fan IEEE Journal of Solid-State Circuits 57 (6), 1736-1748, 2021 | 8 | 2021 |
| Resistor-based Σ-ΔDAC HS Kim, YW Li, A Ravi, H Lakdawala US Patent 8,941,520, 2015 | 7 | 2015 |
| Design of power, dynamic range, bandwidth and noise scalable ADCs B Bakkaloglu, S Kiaei, H Kim, K Chandrashekar Design, Modeling and Testing of Data Converters, 29-81, 2014 | 7 | 2014 |
| A digital fractional-N PLL with a 3mW 0.004mm2 6-bit PVT and mismatch insensitive TDC HS Kim, C Ornelas, K Chandrashekar, P Su, P Madoglio, YW Li, A Ravi 2012 Proceedings of the ESSCIRC (ESSCIRC), 193-196, 2012 | 7 | 2012 |
| A 24GHz CMOS digitally modulated polar power amplifier with embedded FIR filtering H Kim, T Copani, S Kiaei 6th Conference on Ph. D. Research in Microelectronics & Electronics, 1-4, 2010 | 4 | 2010 |
