Yu Cao
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New generation of predictive technology model for sub-45 nm early design exploration
W Zhao, Y Cao
IEEE Transactions on electron Devices 53 (11), 2816-2823, 2006
New paradigm of predictive MOSFET and interconnect modeling for early circuit simulation
Y Cao, T Sato, M Orshansky, D Sylvester, C Hu
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No …, 2000
Throughput-optimized OpenCL-based FPGA accelerator for large-scale convolutional neural networks
N Suda, V Chandra, G Dasika, A Mohanty, Y Ma, S Vrudhula, J Seo, ...
Proceedings of the 2016 ACM/SIGDA international symposium on field …, 2016
Modeling and minimization of PMOS NBTI effect for robust nanometer design
R Vattikonda, W Wang, Y Cao
Proceedings of the 43rd annual Design Automation Conference, 1047-1052, 2006
Predictive modeling of the NBTI effect for reliable design
S Bhardwaj, W Wang, R Vattikonda, Y Cao, S Vrudhula
IEEE Custom Integrated Circuits Conference 2006, 189-192, 2006
Frequency-independent equivalent-circuit model for on-chip spiral inductors
Y Cao, RA Groves, X Huang, ND Zamdmer, JO Plouchart, RA Wachnik, ...
IEEE Journal of solid-state circuits 38 (3), 419-426, 2003
Compact modeling and simulation of circuit reliability for 65-nm CMOS technology
W Wang, V Reddy, AT Krishnan, R Vattikonda, S Krishnan, Y Cao
IEEE Transactions on Device and Materials Reliability 7 (4), 509-517, 2007
Optimizing loop operation and dataflow in FPGA acceleration of deep convolutional neural networks
Y Ma, Y Cao, S Vrudhula, J Seo
Proceedings of the 2017 ACM/SIGDA International Symposium on Field …, 2017
Exploring sub-20nm FinFET design with predictive technology models
S Sinha, G Yeric, V Chandra, B Cline, Y Cao
Proceedings of the 49th Annual Design Automation Conference, 283-288, 2012
The impact of NBTI effect on combinational circuit: Modeling, simulation, and analysis
W Wang, S Yang, S Bhardwaj, S Vrudhula, F Liu, Y Cao
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 18 (2), 173-183, 2009
Optimizing the convolution operation to accelerate deep neural networks on FPGA
Y Ma, Y Cao, S Vrudhula, J Seo
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 26 (7 …, 2018
Reliable systems on unreliable fabrics
T Austin, V Bertacco, S Mahlke, Y Cao
IEEE Design & Test of Computers 25 (4), 322-332, 2008
SRAM leakage suppression by minimizing standby supply voltage
H Qin, Y Cao, D Markovic, A Vladimirescu, J Rabaey
International Symposium on Signals, Circuits and Systems. Proceedings, SCS …, 2004
The impact of NBTI on the performance of combinational and sequential circuits
W Wang, S Yang, S Bhardwaj, R Vattikonda, S Vrudhula, F Liu, Y Cao
Proceedings of the 44th annual Design Automation Conference, 364-369, 2007
Predictive technology model for nano-CMOS design exploration
W Zhao, Y Cao
ACM Journal on Emerging Technologies in Computing Systems (JETC) 3 (1), 1-es, 2007
Modeling within-die spatial correlation effects for process-design co-optimization
P Friedberg, Y Cao, J Cain, R Wang, J Rabaey, C Spanos
Sixth international symposium on quality electronic design (isqed'05), 516-521, 2005
Large-scale neuromorphic spiking array processors: A quest to mimic the brain
CS Thakur, JL Molin, G Cauwenberghs, G Indiveri, K Kumar, N Qiao, ...
Frontiers in neuroscience 12, 891, 2018
Digital circuit design challenges and opportunities in the era of nanoscale CMOS
BH Calhoun, Y Cao, X Li, K Mai, LT Pileggi, RA Rutenbar, KL Shepard
Proceedings of the IEEE 96 (2), 343-365, 2008
Mitigating effects of non-ideal synaptic device characteristics for on-chip learning
PY Chen, B Lin, IT Wang, TH Hou, J Ye, S Vrudhula, J Seo, Y Cao, S Yu
2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 194-199, 2015
Nano-CMOS circuit and physical design
B Wong, A Mittal, Y Cao, GW Starr
John Wiley & Sons, 2005
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