| Testing embedded-core based system chips Y Zorian, EJ Marinissen, S Dey Proceedings International Test Conference 1998 (IEEE Cat. No. 98CH36270 …, 1998 | 772 | 1998 |
| Test wrapper and test access mechanism co-optimization for system-on-chip V Iyengar, K Chakrabarty, EJ Marinissen Journal of Electronic Testing 18 (2), 213-230, 2002 | 479 | 2002 |
| A structured and scalable mechanism for test access to embedded reusable cores EJ Marinissen, R Arendsen, G Bos, H Dingemanse, M Lousberg, ... Proceedings International Test Conference 1998 (IEEE Cat. No. 98CH36270 …, 1998 | 425 | 1998 |
| A set of benchmarks for modular testing of SOCs EJ Marinissen, V Iyengar, K Chakrabarty Proceedings. International Test Conference, 519-528, 2002 | 368 | 2002 |
| Testing 3D chips containing through-silicon vias EJ Marinissen, Y Zorian 2009 International Test Conference, 1-11, 2009 | 362 | 2009 |
| Wrapper design for embedded core test EJ Marinissen, SK Goel, M Lousberg Proceedings International Test Conference 2000 (IEEE Cat. No. 00CH37159 …, 2000 | 315 | 2000 |
| Scan chain design for test time reduction in core-based ICs J Aerts, EJ Marinissen Proceedings International Test Conference 1998 (IEEE Cat. No. 98CH36270 …, 1998 | 245 | 1998 |
| Effective and efficient test architecture design for SOCs SK Goel, EJ Marinissen Proceedings. International Test Conference, 529-538, 2002 | 219 | 2002 |
| Towards a standard for embedded core test: An example EJ Marinissen, Y Zorian, R Kapur, T Taylor, L Whetsel International Test Conference 1999. Proceedings (IEEE Cat. No. 99CH37034 …, 1999 | 212 | 1999 |
| On using rectangle packing for SOC wrapper/TAM co-optimization V Iyengar, K Chakrabarty, EJ Marinissen Proceedings 20th IEEE VLSI Test Symposium (VTS 2002), 253-258, 2002 | 207 | 2002 |
| A structured and scalable test access architecture for TSV-based 3D stacked ICs EJ Marinissen, J Verbree, M Konijnenburg 2010 28th VLSI Test Symposium (VTS), 269-274, 2010 | 177 | 2010 |
| On IEEE P1500’s standard for embedded core test EJ Marinissen, R Kapur, M Lousberg, T McLaurin, M Ricchetti, Y Zorian, ... SOC (System-on-a-Chip) Testing for Plug and Play Test Automation, 1-19, 2002 | 169 | 2002 |
| Test access mechanism optimization, test scheduling, and tester data volume reduction for system-on-chip K Chakrabarty, EJ Marinissen IEEE Transactions on Computers 52 (12), 1619-1632, 2003 | 150 | 2003 |
| SOC test architecture design for efficient utilization of test bandwidth SK Goel, EJ Marinissen ACM Transactions on Design Automation of Electronic Systems (TODAES) 8 (4 …, 2003 | 118 | 2003 |
| Challenges in embedded memory design and test EJ Marinissen, B Prince, D Keltel-Schulz, Y Zorian Design, Automation and Test in Europe, 722-727, 2005 | 115 | 2005 |
| Challenges and emerging solutions in testing TSV-based 2 1 over 2D-and 3D-stacked ICs EJ Marinissen 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2012 | 109 | 2012 |
| Application of deterministic logic BIST on industrial circuits G Kiefer, H Vranken, EJ Marinissen, HJ Wunderlich Journal of Electronic Testing 17 (3-4), 351-362, 2001 | 109 | 2001 |
| Impact of 3D design choices on manufacturing cost D Velenis, M Stucchi, EJ Marinissen, B Swinnen, E Beyne 2009 IEEE International Conference on 3D System Integration, 1-5, 2009 | 108 | 2009 |
| Efficient wrapper/TAM co-optimization for large SOCs V Iyengar, K Chakrabarty, EJ Marinissen Proceedings 2002 Design, Automation and Test in Europe Conference and …, 2002 | 107 | 2002 |
| Testing TSV-based three-dimensional stacked ICs EJ Marinissen 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010 …, 2010 | 105 | 2010 |
Sandeep Kumar GoelAcademician/Deputy Director, TSMCVerified email at tsmc.com
