| System margining surrogate-based optimization in post-silicon validation FE Rangel-Patiño, JL Chávez-Hurtado, A Viveros-Wacher, ... IEEE Transactions on Microwave Theory and Techniques 65 (9), 3109-3115, 2017 | 30 | 2017 |
| Post-silicon receiver equalization metamodeling by artificial neural networks FE Rangel-Patiño, JE Rayas-Sánchez, A Viveros-Wacher, ... IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2018 | 25 | 2018 |
| Analog fault identification in RF circuits using artificial neural networks and constrained parameter extraction A Viveros-Wacher, JE Rayas-Sánchez 2018 IEEE MTT-S International Conference on Numerical Electromagnetic and …, 2018 | 21 | 2018 |
| A holistic formulation for system margining and jitter tolerance optimization in industrial post-silicon validation FE Rangel-PatiÑo, A Viveros-Wacher, JE Rayas-Sánchez, ... IEEE Transactions on Emerging Topics in Computing 8 (2), 453-463, 2017 | 18 | 2017 |
| A holistic methodology for system margining and jitter tolerance optimization in post-silicon validation FE Rangel-Patiño, A Viveros-Wacher, JE Rayas-Sánchez, ... 2016 IEEE MTT-S Latin America Microwave Conference (LAMC), 1-4, 2016 | 18 | 2016 |
| Analog gross fault identification in RF circuits using neural models and constrained parameter extraction A Viveros-Wacher, JE Rayas-Sánchez, Z Brito-Brito IEEE Transactions on Microwave Theory and Techniques 67 (6), 2143-2150, 2019 | 14 | 2019 |
| SMV methodology enhancements for high speed I/O links of SoCs A Viveros-Wacher, R Alejos, L Alvarez, I Diaz-Castro, B Marcial, ... 2014 IEEE 32nd VLSI Test Symposium (VTS), 1-5, 2014 | 10 | 2014 |
| High-speed links receiver optimization in post-silicon validation exploiting Broyden-based input space mapping FE Rangel-Patiño, JE Rayas-Sánchez, A Viveros-Wacher, ... 2018 IEEE MTT-S International Conference on Numerical Electromagnetic and …, 2018 | 8 | 2018 |
| Eye diagram optimization based on design of experiments (DoE) to accelerate industrial testing of high speed links A Viveros-Wacher, JE Rayas-Sánchez 2016 IEEE MTT-S Latin America Microwave Conference (LAMC), 1-3, 2016 | 8 | 2016 |
| Eye diagram system margining surrogate-based optimization in a server silicon validation platform FE Rangel-Patiño, JL Chávez-Hurtado, A Viveros-Wacher, ... EuMA, 2017 | 7 | 2017 |
| Jitter tolerance acceleration using the golden section optimization technique A Viveros-Wacher, R Baca-Baylón, FE Rangel-Patiño, ... 2018 IEEE 9th Latin American Symposium on Circuits & Systems (LASCAS), 1-4, 2018 | 5 | 2018 |
| Fast jitter tolerance testing for high-speed serial links in post-silicon validation A Viveros-Wacher, R Baca-Baylón, FE Rangel-Patiño, JL Silva-Cortés, ... IEEE Transactions on Electromagnetic Compatibility 64 (2), 516-523, 2021 | 2 | 2021 |
| Industry-oriented research projects on computer-aided design of high-frequency circuits and systems at ITESO Mexico JE Rayas-Sánchez, FE Rangel-Patiño, A Viveros-Wacher, ... EuMA, 2018 | 2 | 2018 |
| PCIe Gen5 physical layer equalization tuning by using K-means clustering and Gaussian process regression modeling in industrial post-silicon validation FE Rangel-Patiño, A Viveros-Wacher, C Rajyaguru, EA Vega-Ochoa, ... 2023 IEEE MTT-S International Conference on Numerical Electromagnetic and …, 2023 | 1 | 2023 |
| High Speed Serial Links Risk Assessment in Industrial Post-Silicon Validation Exploiting Machine Learning Techniques CA Sánchez-Martínez, P López-Meyer, E Juarez-Hernandez, ... 2020 IEEE International Test Conference (ITC), 1-5, 2020 | 1 | 2020 |
| PCIe Gen6 Physical Layer Equalization Tuning by Using Unsupervised and Supervised Machine Learning Techniques FE Rangel-Patiño, A Viveros-Wacher, SD Rodriguez-Saenz, ... 2023 IEEE MTT-S Latin America Microwave Conference (LAMC), 105-108, 2023 | | 2023 |
| Equalization Tuning of the PCIe Physical Layer by Using Machine Learning in Industrial Post-silicon Validation FE Rangel-Patiño, A Viveros-Wacher, C Rajyaguru, EA Vega-Ochoa, ... IEEE, 2023 | | 2023 |
| Machine Learning Techniques and Optimization Approaches for Analog Validation and Testing A Viveros-Wacher ITESO, 2020 | | 2020 |
| THIS ISSUE INCLUDES THE JOURNAL WITHIN A JOURNAL ON MICROWAVE SYSTEMS AND APPLICATIONS MINI-SPECIAL ISSUE ON 2016 IEEE MTT-S LATIN AMERICA MICROWAVE CONFERENCE (LAMC 2016) PV Testa, C Carta, M Barahona, F Ellinger, EA Rojas-Nastrucci, ... | | |
