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Aditya Yanamandra
Aditya Yanamandra
Component Design Engineer, Intel Corporation
Verified email at intel.com
Title
Cited by
Cited by
Year
A low-power phase change memory based hybrid cache architecture
P Mangalagiri, K Sarpatwari, A Yanamandra, VK Narayanan, Y Xie, ...
Proceedings of the 18th ACM Great Lakes symposium on VLSI, 395-398, 2008
862008
On the effects of process variation in network-on-chip architectures
C Nicopoulos, S Srinivasan, A Yanamandra, D Park, V Narayanan, ...
IEEE Transactions on Dependable and Secure Computing 7 (3), 240-254, 2008
692008
RAFT: A router architecture with frequency tuning for on-chip networks
AK Mishra, A Yanamandra, R Das, S Eachempati, R Iyer, N Vijaykrishnan, ...
Journal of Parallel and Distributed Computing 71 (5), 625-640, 2011
372011
Optimizing power and performance for reliable on-chip networks
A Yanamandra, S Eachempati, N Soundararajan, V Narayanan, MJ Irwin, ...
2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC), 431-436, 2010
202010
Evaluating the role of scratchpad memories in chip multiprocessors for sparse matrix computations
A Yanamandra, B Cover, P Raghavan, MJ Irwin, M Kandemir
2008 IEEE International Symposium on Parallel and Distributed Processing, 1-10, 2008
122008
Variation-aware low-power buffer design
C Nicopoulos, A Yanamandra, S Srinivasan, N Vijaykrishnan, MJ Irwin
2007 Conference Record of the Forty-First Asilomar Conference on Signals …, 2007
122007
In-network caching for chip multiprocessors
A Yanamandra, MJ Irwin, V Narayanan, M Kandemir, SHK Narayanan
International Conference on High-Performance Embedded Architectures and …, 2009
82009
Analysis and solutions to issue queue process variation
N Soundararajan, A Yanamandra, C Nicopoulos, N Vijaykrishnan, ...
2008 IEEE International Conference on Dependable Systems and Networks With …, 2008
52008
Power and area reduction using carbon nanotube bundle interconnect in global clock tree distribution network
Y Xie, S Eachempati, A Yanamandra, V Narayanan, MJ Irwin
2009 IEEE/ACM International Symposium on Nanoscale Architectures, 51-56, 2009
22009
Exploring Power Reliability Tradeoffs in On-Chip Networks
A Yanamandra
2010
Reliability Aware Performance and Power Optimization in DVFS-Based On-Chip Networks
A Yanamandra, S Eachempati, V Narayanan, MJ Irwin
Dynamic Reconfigurable Network-on-Chip Design: Innovations for Computational …, 2010
2010
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Articles 1–11