| Butterfly and Benes-based on-chip communication networks for multiprocessor turbo decoding H Moussa, O Muller, A Baghdadi, M Jézéquel 2007 Design, Automation & Test in Europe Conference & Exhibition, 1-6, 2007 | 80 | 2007 |
| From parallelism levels to a multi-ASIP architecture for turbo decoding O Muller, A Baghdadi, M Jézéquel IEEE transactions on very large scale integration (VLSI) systems 17 (1), 92-102, 2008 | 66 | 2008 |
| ASIP-based multiprocessor SoC design for simple and double binary turbo decoding O Muller, A Baghdadi, M Jézéquel Proceedings of the Design Automation & Test in Europe Conference 1, 1-6, 2006 | 66 | 2006 |
| Exploring parallel processing levels for convolutional turbo decoding O Muller, A Baghdadi, M Jezequel 2006 2nd International Conference on Information & Communication …, 2006 | 61 | 2006 |
| Fast and standalone design space exploration for high-level synthesis under resource constraints A Prost-Boucle, O Muller, F Rousseau Journal of Systems Architecture 60 (1), 79-93, 2014 | 49 | 2014 |
| Parallelism efficiency in convolutional turbo decoding O Muller, A Baghdadi, M Jézéquel EURASIP journal on advances in signal processing 2010, 1-11, 2010 | 22 | 2010 |
| A fast and autonomous HLS methodology for hardware accelerator generation under resource constraints A Prost-Boucle, O Muller, F Rousseau 2013 Euromicro Conference on Digital System Design, 201-208, 2013 | 21 | 2013 |
| On the parallelism of convolutional turbo decoding and interleaving interference O Muller, A Baghdadi, M Jézéquel Global Telecommunications Conference, 2006. GLOBECOM'06. IEEE, 1-5, 2006 | 16* | 2006 |
| Automatic high-level hardware checkpoint selection for reconfigurable systems A Bourge, O Muller, F Rousseau 2015 IEEE 23rd Annual International Symposium on Field-Programmable Custom …, 2015 | 15 | 2015 |
| Architectures multiprocesseurs monopuces génériques pour turbo-communications haut-débit O Muller Université de Bretagne Sud, 2007 | 15 | 2007 |
| From application to ASIP-based FPGA prototype: a case study on turbo decoding O Muller, A Baghdadi, M Jézéquel 2008 The 19th IEEE/IFIP International Symposium on Rapid System Prototyping …, 2008 | 14 | 2008 |
| HCM: An abstraction layer for seamless programming of DPR FPGA Y Xu, O Muller, PH Horrein, F Pétrot 22nd International Conference on Field Programmable Logic and Applications …, 2012 | 11 | 2012 |
| Bandwidth reduction of extrinsic information exchange in turbo decoding O Muller, A Baghdadi, M Jézéquel Electronics Letters 42 (19), 1104-1106, 2006 | 11 | 2006 |
| A Fast and Stand-alone HLS Methodology for Hardware Accelerator Generation Under Resource Constraints A Prost-Boucle, O Muller, F Rousseau HLS4HPC workshop, HiPEAC conference, 0 | 2* | |
| A Novel Method for Enabling FPGA Context-Switch A Bourge, O Muller, F Rousseau Proceedings of the 2015 ACM/SIGDA International Symposium on Field …, 2015 | | 2015 |
| Méthode de sélection de checkpoint matériel avec outil de synthese de haut niveau A Bourge, A Ghiti, O Muller, F Rousseau Journées Nationales du Réseau Doctoral en Microélectronique (JNRDM'14), 4, 2014 | | 2014 |
| Compression de configuration FPGA S Marijon, O Muller, PH Horrein | | 2012 |
| FPGA Prototypes for Turbo Communication Applications C Jego, A Baghdadi, C Leroux, H Moussa, O Muller, AR Jafri, O Al Assil, ... University Booth of DATE 09: Design, Automation & Test in Europe Conference …, 2009 | | 2009 |
| Flexible Multi-ASIP SoC for High-Throughput Turbo Decoders O Muller, A Baghdadi, M Jezequel Premier Colloque National du GDR SOC-SIP, ., 2007 | | 2007 |
| DSD call for paper, Special Session on Flexible Digital Radio (FDR) D Noguet, A Baghdadi, I Dayoub, L Fanucci, A Gelonch, A Ghazel, ... | | |
Frédéric PétrotTIMA Lab, Université Grenoble Alpes, Grenoble Institute of EngineeringVerified email at univ-grenoble-alpes.fr
