| Algorithms for state restoration and trace-signal selection for data acquisition in silicon debug HF Ko, N Nicolici IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2009 | 401 | 2009 |
| On using lossless compression of debug data in embedded logic analysis E Anis, N Nicolici 2007 IEEE International Test Conference, 1-10, 2007 | 347 | 2007 |
| Low cost debug architecture using lossy compression for silicon debug E Anis, N Nicolici 2007 Design, Automation & Test in Europe Conference & Exhibition, 1-6, 2007 | 340 | 2007 |
| Power-aware testing and test strategies for low power devices P Girard, N Nicolici, X Wen Springer Science & Business Media, 2010 | 300 | 2010 |
| Distributed embedded logic analysis for post-silicon validation of SOCs HF Ko, AB Kinsman, N Nicolici 2008 IEEE International Test Conference, 1-10, 2008 | 296 | 2008 |
| Resource-efficient programmable trigger units for post-silicon validation HF Ko, N Nicolici 2009 14th IEEE European Test Symposium, 17-22, 2009 | 264 | 2009 |
| Variable-length input Huffman coding for system-on-a-chip test PT Gonciari, BM Al-Hashimi, N Nicolici IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2003 | 263 | 2003 |
| Design-for-debug for post-silicon validation: Can high-level descriptions help? N Nicolici, HF Ko 2009 IEEE International High Level Design Validation and Test Workshop, 172-175, 2009 | 254 | 2009 |
| Functional scan chain design at RTL for skewed-load delay fault testing HF Ko, N Nicolici 13th Asian Test Symposium, 454-459, 2004 | 248 | 2004 |
| Scan architecture with mutually exclusive scan segment activation for shift-and capture-power reduction P Rosinger, BM Al-Hashimi, N Nicolici IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2004 | 240 | 2004 |
| Post-silicon validation opportunities, challenges and recent advances S Mitra, SA Seshia, N Nicolici Proceedings of the 47th Design Automation Conference, 12-17, 2010 | 210 | 2010 |
| Improving compression ratio, area overhead, and test application time for system-on-a-chip test data compression/decompression PT Gonciari, BM Al-Hashimi, N Nicolici Proceedings 2002 Design, Automation and Test in Europe Conference and …, 2002 | 183 | 2002 |
| Power-constrained testing of VLSI circuits N Nicolici, B Al-Hashimi Kluwer Academic Publishers, 2003 | 140 | 2003 |
| Automated trace signals identification and state restoration for improving observability in post-silicon validation HF Ko, N Nicolici Proceedings of the conference on Design, automation and test in Europe, 1298 …, 2008 | 137 | 2008 |
| Low power mixed-mode BIST based on mask pattern generation using dual LFSR re-seeding PM Rosinger, BM Al-Hashimi, N Nicolici Proceedings. IEEE International Conference on Computer Design: VLSI in …, 2002 | 74 | 2002 |
| Minimisation of power dissipation during test application in full-scan sequential circuits using primary input freezing N Nicolici, BM Al-Hashimi, AC Williams IEE Proceedings-Computers and Digital Techniques 147 (5), 313-322, 2000 | 74 | 2000 |
| Resource-constrained system-on-a-chip test: a survey Q Xu, N Nicolici IEE Proceedings-Computers and Digital Techniques 152 (1), 67-81, 2005 | 69 | 2005 |
| Multiple scan chains for power minimization during test application in sequential circuits N Nicolici, BM Al-Hashimi IEEE Transactions on Computers 51 (6), 721-734, 2002 | 64 | 2002 |
| Simultaneous reduction in volume of test data and power dissipation for systems-on-a-chip P Rosinger, PT Gonciari, BM Al-Hashimi, N Nicolici Electronics Letters 37 (24), 1434-1436, 2001 | 62 | 2001 |
| Scan architecture for shift and capture cycle power reduction PM Rosinger, BM Al-Hashimi, N Nicolici 17th IEEE International Symposium on Defect and Fault Tolerance in VLSI …, 2002 | 57 | 2002 |
Bashir M. Al-HashimiProfessor of Computer Engineering, King’s College LondonVerified email at kcl.ac.uk
