Vikas Chandra
Vikas Chandra
Director, AI @ Meta Reality Labs, Facebook
Verified email at - Homepage
Cited by
Cited by
Federated Learning with Non-IID Data
Y Zhao, M Li, L Lai, N Suda, D Civin, V Chandra
arXiv preprint arXiv:1806.00582, 2018
Throughput-optimized OpenCL-based FPGA Accelerator for Large-scale Convolutional Neural Networks
N Suda, V Chandra, G Dasika, A Mohanty, Y Ma, S Vrudhula, J Seo, ...
Proceedings of the 2016 ACM/SIGDA International Symposium on Field …, 2016
Bit fusion: Bit-level Dynamically Composable Architecture for Accelerating Deep Neural Network
H Sharma, J Park, N Suda, L Lai, B Chau, V Chandra, H Esmaeilzadeh
2018 ACM/IEEE 45th Annual International Symposium on Computer Architecture …, 2018
Hello Edge: Keyword Spotting on Microcontrollers
Y Zhang, N Suda, L Lai, V Chandra
arXiv preprint arXiv:1711.07128, 2017
Exploring Sub-20nm FinFET Design with Predictive Technology Models
S Sinha, G Yeric, V Chandra, B Cline, Y Cao
DAC Design Automation Conference 2012, 283-288, 2012
CMSIS-NN: Efficient Neural Network Kernels for Arm Cortex-M CPUs
L Lai, N Suda, V Chandra
arXiv preprint arXiv:1801.06601, 2018
Impact of Technology and Voltage Scaling on the Soft Error Susceptibility in Nanoscale CMOS
V Chandra, R Aitken
2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI …, 2008
Configurable IC with Interconnect Circuits that also Perform Storage Operations
S Teig, H Schmit, J Redgrave, V Chandra
US Patent 7,342,415, 2008
FPGA Switch Block Layout and Evaluation
H Schmit, V Chandra
Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field …, 2002
TIMBER: Time Borrowing and Error Relaying for Online Timing Error Resilience
M Choudhury, V Chandra, K Mohanram, R Aitken
2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010 …, 2010
RecNMP: Accelerating Personalized Recommendation with Near-Memory Processing
L Ke, U Gupta, BY Cho, D Brooks, V Chandra, U Diril, A Firoozshahian, ...
2020 ACM/IEEE 47th Annual International Symposium on Computer Architecture …, 2020
Deep Convolutional Neural Network Inference with Floating-point Weights and Fixed-point Activations
L Lai, N Suda, V Chandra
arXiv preprint arXiv:1703.03073, 2017
Correlated Electron Switch Programmable Fabric
L Shifren, G Yeric, S Sinha, B Cline, V Chandra
US Patent 10,056,143, 2018
Co-Exploration of Neural Architectures and Heterogeneous ASIC Accelerator Designs Targeting Multiple Tasks
L Yang, Z Yan, M Li, H Kwon, L Lai, T Krishna, V Chandra, W Jiang, Y Shi
2020 57th ACM/IEEE Design Automation Conference (DAC), 1-6, 2020
Device and Technology Implications of the Internet of Things
R Aitken, V Chandra, J Myers, B Sandhu, L Shifren, G Yeric
2014 symposium on VLSI technology (VLSI-technology): digest of technical …, 2014
Workload dependent NBTI and PBTI analysis for a sub-45nm commercial microprocessor
E Mintarno, V Chandra, D Pietromonaco, R Aitken, RW Dutton
2013 IEEE International Reliability Physics Symposium (IRPS), 3A. 1.1-3A. 1.6, 2013
On the Efficacy of Write-Assist Techniques in Low Voltage Nanoscale SRAMs
V Chandra, C Pietrzyk, R Aitken
2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010 …, 2010
Heterogeneous Dataflow Accelerators for Multi-DNN Workloads
H Kwon, L Lai, M Pellauer, T Krishna, YH Chen, V Chandra
2021 IEEE International Symposium on High-Performance Computer Architecture …, 2021
Analytical Model for TDDB-based Performance Degradation in Combinational Logic
M Choudhury, V Chandra, K Mohanram, R Aitken
2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010 …, 2010
Comprehensive Analysis of Sequential and Combinational Soft Errors in an Embedded Processor
M Ebrahimi, A Evans, MB Tahoori, E Costenaro, D Alexandrescu, ...
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2015
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