| SCAFFI: An intrachip FPGA asynchronous interface based on hard macros J Pontes, R Soares, E Carvalho, F Moraes, N Calazans 2007 25th International Conference on Computer Design, 541-546, 2007 | 50 | 2007 |
| Hermes-glp: A gals network on chip router with power control techniques J Pontes, M Moreira, R Soares, N Calazans 2008 IEEE Computer Society Annual Symposium on VLSI, 347-352, 2008 | 44 | 2008 |
| Evaluating the robustness of secure triple track logic through prototyping R Soares, N Calazans, V Lomné, P Maurine, L Torres, M Robert Proceedings of the 21st annual symposium on Integrated circuits and system …, 2008 | 40 | 2008 |
| Evaluation on FPGA of triple rail logic robustness against DPA and DEMA V Lomné, P Maurine, L Torres, M Robert, R Soares, N Calazans 2009 Design, Automation & Test in Europe Conference & Exhibition, 634-639, 2009 | 33 | 2009 |
| A robust architectural approach for cryptographic algorithms using GALS pipelines R Soares, N Calazans, F Moraes, P Maurine, L Torres IEEE Design & Test of Computers 28 (5), 62-71, 2011 | 24 | 2011 |
| A NoC-based infrastructure to enable dynamic self reconfigurable systems L Möller, I Grehs, E Carvalho, R Soares, N Calazans, F Moraes Dynamic Reconfigurable Network-on-Chip Design: Innovations for Computational …, 2010 | 22 | 2010 |
| Infrastructure for dynamic reconfigurable systems: choices and trade-offs L Möller, R Soares, E Carvalho, I Grehs, N Calazans, F Moraes Proceedings of the 19th annual symposium on Integrated circuits and systems …, 2006 | 21 | 2006 |
| HardNoC: A platform to validate networks on chip through FPGA prototyping G Heck, R Guazzelli, F Moraes, N Calazans, R Soares 2012 VIII Southern Conference on Programmable Logic, 1-6, 2012 | 16 | 2012 |
| An energy-based attack flow for temporal misalignment coutermeasures on cryptosystems R Lellis, RI Soares, A Souza 2017 IEEE International Symposium on Circuits and Systems (ISCAS), 1-4, 2017 | 9 | 2017 |
| A semi-passive UHF RFID tag compliant with Brazilian national automated vehicle identification system (SINIAV) EH Neto, R Soares, E Conrad, J Costa, M Ramaswami 2012 IEEE International Conference on RFID-Technologies and Applications …, 2012 | 8 | 2012 |
| Identification and frequency of transposable elements in Eucalyptus M Bacci Jr, R Soares, E Tajara, G Ambar, CN Fischer, IR Guilherme, ... Genetics and Molecular Biology 28 (3), 634-639, 2005 | 7 | 2005 |
| A GALS Pipeline DES Architecture to Increase Robustness Against CPA and CEMA Attacks P Maurine, RI Soares, NLV Calazans, V Lomné, A Dehbaoui, L Torres Journal of Integrated Circuits and Systems 5, 001-010, 2011 | 6* | 2011 |
| A GALS pipeline DES architecture to increase robustness against DPA and DEMA attacks RI Soares, NLV Calazans, V Lomné, A Dehbaoui, P Maurine, L Torres Proceedings of the 23rd symposium on Integrated circuits and system design …, 2010 | 6 | 2010 |
| Low voltage low power current reference circuit for passive RFID applications DM Colombo, R Soares, F Mattos 2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS), 107-110, 2016 | 5 | 2016 |
| Towards a framework to perform DPA attack on GALS pipeline architectures L Loder, A de Souza, M Fay, R Soares 2014 27th Symposium on Integrated Circuits and Systems Design (SBCCI), 1-7, 2014 | 5 | 2014 |
| Secure triple track logic robustness against differential power and electromagnetic analyses V Lomné, A Dehbaoui, T Ordas, P Maurine, L Torres, M Robert, R Soares, ... Journal of Integrated Circuits and Systems 4 (1), 20-28, 2009 | 4 | 2009 |
| Arquitetura GALS pipeline para criptografia robusta a ataques DPA e DEMA RI Soares Pontifícia Universidade Católica do Rio Grande do Sul, 2010 | 3 | 2010 |
| Triple Rail Logic Robustness against DPA V Lomné, T Ordas, P Maurine, L Torres, M Robert, R Soares, N Calazans 2008 International Conference on Reconfigurable Computing and FPGAs, 415-420, 2008 | 2 | 2008 |
| Enhancing Side Channel Attack-Resistance of the STTL Combining Multi-Vt Transistors with Capacitance and Current Paths Counterbalancing VG Lima, G Paim, R Wuerdig, LMG Rocha, L da Rosa Júnior, F Marques, ... Journal of Integrated Circuits and Systems 15 (1), 1-11, 2020 | 1 | 2020 |
| Maximizing Side Channel Attack-Resistance and Energy-Efficiency of the STTL Combining Multi-Vt Transistors with Current and Capacitance Balancing VG Lima, G Paim, LMG Rocha, L da Rosa, F Marques, EAC da Costa, ... 2019 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2019 | 1 | 2019 |
Ney Laert Vilar CalazansInvited Researcher at the Graduate Program on Microelectronics (PGMICRO), UFRGSVerified email at inf.ufrgs.br
