| 21.1 A 1.7 GHz MDLL-based fractional-N frequency synthesizer with 1.4 ps RMS integrated jitter and 3mW power using a 1b TDC G Marucci, A Fenaroli, G Marzin, S Levantino, C Samori, AL Lacaita 2014 IEEE International Solid-State Circuits Conference Digest of Technical …, 2014 | 72 | 2014 |
| Analysis and design of low-jitter digital bang-bang phase-locked loops G Marucci, S Levantino, P Maffezzoni, C Samori IEEE Transactions on Circuits and Systems I: Regular Papers 61 (1), 26-36, 2013 | 64 | 2013 |
| A 1.7 GHz fractional-N frequency synthesizer based on a multiplying delay-locked loop S Levantino, G Marucci, G Marzin, A Fenaroli, C Samori, AL Lacaita IEEE Journal of Solid-State Circuits 50 (11), 2678-2691, 2015 | 63 | 2015 |
| Stochastic testing simulator for integrated circuits and MEMS: Hierarchical and sparse techniques Z Zhang, X Yang, G Marucci, P Maffezzoni, IAM Elfadel, G Karniadakis, ... Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 1-8, 2014 | 34 | 2014 |
| Exploiting stochastic resonance to enhance the performance of digital bang-bang PLLs G Marucci, S Levantino, P Maffezzoni, C Samori IEEE Transactions on Circuits and Systems II: Express Briefs 60 (10), 632-636, 2013 | 29 | 2013 |
| The Italian Pilot Project LabTec of the Ministry of Education G Marucci, M Michelini, LG Santi Physics Teacher Education Beyond 2000 (Phyteb 2000), 607-610, 2001 | 24 | 2001 |
| A spur cancellation technique for MDLL-based frequency synthesizers G Marzin, A Fenaroli, G Marucci, S Levantino, C Samori, AL Lacaita 2013 IEEE International Symposium on Circuits and Systems (ISCAS), 165-168, 2013 | 8 | 2013 |
| Fast frequency hopping phase locked loop M Zanuso, G Marucci, TP Hung, F Gatta, B Sun US Patent 10,063,366, 2018 | 5 | 2018 |
| Comparing techniques for spur reduction in digital bang‐bang PLLs P Maffezzoni, G Marucci, S Levantino, C Samori Electronics letters 49 (8), 527-529, 2013 | 3 | 2013 |
| Techniques for high-efficiency digital frequency synthesis G Marucci Politecnico di Milano, 2015 | 2 | 2015 |
| Minimum-jitter design of bang-bang PLLs in the presence of 1/f2 and 1/f3 DCO noise G Marucci, S Levantino, P Maffezzoni, C Samori 2013 IEEE International Symposium on Circuits and Systems (ISCAS), 173-176, 2013 | 1 | 2013 |
| Phase interpolation-based fractional-N sampling phase-locked loop MM Bajestan, G Marucci, D Park, M Zanuso, Y Tang US Patent 11,411,567, 2022 | | 2022 |
| An efficient method to compute phase-noise in injection-locked frequency dividers G Marucci, S Levantino, P Maffezzoni, C Samori 2013 IEEE International Symposium on Circuits and Systems (ISCAS), 1753-1756, 2013 | | 2013 |
| Progetto di un amplificatore di potenza RF in classe D per trasmettitori polari in tecnologia CMOS 65nm G MARUCCI Politecnico di Milano, 2010 | | 2010 |
| Le tecnologie dell’informazione per il laboratorio didattico: innovazione didattica e formazione degli insegnanti nel progetto pilota LabTec1 G Marucci, M Michelini, L Santi Nuovi obiettivi, curricoli e metodologie nella didattica della matematica e …, 2002 | | 2002 |
| Il Progetto Labtec/1: insegnamento scientifico-tecnologico integrato con le nuove tecnologie G Marucci, M Michelini Quaderno MPI 39, 250-250, 2001 | | 2001 |
| The Italian pilot Project of the Italian Ministerium of Education G Marucci, M Michelini, L SANTI | | 2000 |
Maffezzoni PaoloProfessor of Electrical Engineering, Politecnico di Milano, ItalyVerified email at polimi.it
