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Toshinori Sato
Toshinori Sato
Fukuoka University
Verified email at computer.org - Homepage
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Cited by
Cited by
Year
A simple flip-flop circuit for typical-case designs for DFM
T Sato, Y Kunitake
8th International Symposium on Quality Electronic Design (ISQED'07), 539-544, 2007
1802007
Evaluation of architecture-level power estimation for CMOS RISC processors
T Sato, Y Ootaguro, M Nagamatsu, H Tago
1995 IEEE Symposium on Low Power Electronics. Digest of Technical Papers, 44-45, 1995
821995
2.44-GFLOPS 300-MHz floating-point vector-processing unit for high-performance 3D graphics computing
N Ide, M Hirano, Y Endo, S Yoshioka, H Murakami, A Kunimatsu, T Sato, ...
IEEE Journal of Solid-State Circuits 35 (7), 1025-1033, 2000
752000
An efficient algorithm for layout compaction problem with symmetry constraints
R Okuda, T Sato, H Onodera, K Tamariu
Computer-Aided Design, 1989. ICCAD-89. Digest of Technical Papers., 1989 …, 1989
711989
Power and performance simulator: ESP and its application for 100 MIPS/W class RISC design
T Sato, M Nagamatsu, H Tago
Proceedings of 1994 IEEE Symposium on Low Power Electronics, 46-47, 1994
631994
Vector unit architecture for emotion synthesis
A Kunimatsu, N Ide, T Sato, Y Endo, H Murakami, T Kamei, M Hirano, ...
IEEE Micro 20 (2), 40-47, 2000
582000
Table size reduction for data value predictors by exploiting narrow width values
T Sato, I Arita
Proceedings of the 14th international conference on Supercomputing, 196-205, 2000
502000
A low-power high-speed accuracy-controllable approximate multiplier design
T Yang, T Ukezono, T Sato
2018 23rd Asia and South Pacific design automation conference (ASP-DAC), 605-610, 2018
462018
Low-power and high-speed approximate multiplier design with a tree compressor
T Yang, T Ukezono, T Sato
2017 IEEE International Conference on Computer Design (ICCD), 89-96, 2017
452017
A Low-Power Configurable Adder for Approximate Applications
T Yang, T Ukezono, T Sato
19th International Symposium on Quality Electronic Design, 347-352, 2018
442018
Speculative execution of a load instruction by associating the load instruction with a previously executed store instruction
T Sato
US Patent 6,415,380, 2002
382002
Data dependence speculation using data address prediction and its enhancement with instruction reissue
T Sato
Proceedings. 24th EUROMICRO Conference (Cat. No. 98EX204) 1, 285-292, 1998
361998
Processor provided with a data value prediction circuit and a branch prediction circuit
T Sato
US Patent 6,516,409, 2003
352003
Analyzing overhead of reissued instructions on data speculative processors
T Sato
Workshop on Performance Analysis and its Impact on Design, held in …, 1998
311998
Signal probability control for relieving NBTI in SRAM cells
Y Kunitake, T Sato, H Yasuura
2010 11th International symposium on quality electronic design (ISQED), 660-666, 2010
302010
AMPLE: An adaptive multi-performance processor for low-energy embedded applications
T Ishihara, S Yamaguchi, Y Ishitobi, T Matsumura, Y Kunitake, Y Oyama, ...
2008 Symposium on Application Specific Processors, 83-88, 2008
282008
Constructive timing violation for improving energy efficiency
T Sato, I Arita
Compilers and operating systems for low power, 137-153, 2003
282003
Revisiting direct tag search algorithm on superscalar processors
T Sato, Y Nakamura, I Arita
Workshop on Complexity-Effective Design, 2001
272001
Dependability, power, and performance trade-off on a multicore processor
T Sato, T Funaki
2008 Asia and South Pacific Design Automation Conference, 714-719, 2008
242008
Possibilities to miss predicting timing errors in canary flip-flops
Y Kunitake, T Sato, H Yasuura, T Hayashida
2011 IEEE 54th International Midwest Symposium on Circuits and Systems …, 2011
232011
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